Intel corporation (20240427847). SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS

Organization Name

intel corporation

Inventor(s)

SUBRAMANIAM Maiyuran of GOLD RIVER CA (US)

JORGE Parra of EL DORADO HILLS CA (US)

SUPRATIM Pal of BANGALORE (IN)

ASHUTOSH Garg of FOLSOM CA (US)

SHUBRA Marwaha of FOLSOM CA (US)

CHANDRA Gurram of FOLSOM CA (US)

DARIN Starkey of ROSEVILLE CA (US)

DURGESH Borkar of FOLSOM CA (US)

VARGHESE George of FOLSOM CA (US)

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS

This abstract first appeared for US patent application 20240427847 titled 'SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS

Original Abstract Submitted

described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.