TEST ARCHITECTURE FOR 3D STACKED CIRCUITS: abstract simplified (17700329)

The abstract describes a configuration of stacked circuits that are designed to make testing after stacking easier. In this configuration, there are two dies (individual circuit components) that are connected through multiple interconnects. The first die has interfaces for receiving test data signals and a clock signal, as well as interfaces for conveying test responses. It also has pathways for transmitting test signals and clock signals to the second die with low latency. The second die has interfaces for receiving test responses and clock signals from the first die. The abstract mentions that there are other aspects and features included in this configuration, but does not provide further details.