18229705. READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE (Western Digital Technologies, Inc.)
Contents
READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE
Organization Name
Western Digital Technologies, Inc.
Inventor(s)
Xiang Yang of Santa Clara CA (US)
Albert Chen of Milpitas CA (US)
Jonathan Huynh of San Jose CA (US)
READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE
This abstract first appeared for US patent application 18229705 titled 'READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE
Original Abstract Submitted
An apparatus comprising a set of memory cells and a control circuit coupled to the set of memory cells is disclosed. The control circuit is configured to: transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level; subsequent to transitioning the wordline voltage to the second wordline voltage level, ramp down a bitline voltage of a bitline associated with the target memory cell from a first bitline voltage level to a second bitline voltage level; and prior to sensing a state of the memory cell, ramp up the bitline voltage from the second bitline voltage level to the first bitline voltage level.
