Taiwan semiconductor manufacturing company, ltd. (20240379846). FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING simplified abstract
Contents
FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Hung-Li Chiang of Taipei City (TW)
Chih-Sheng Chang of Hsinchu (TW)
Tzu-Chiang Chen of Hsinchu City (TW)
FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240379846 titled 'FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING
Simplified Explanation: The patent application describes an innovative structure for a MOSFET-FET (MFMIS-FET) that increases the effective area of the MOSFET without increasing its footprint. By uniting the gate electrode of the MOSFET and the bottom electrode of the MFM, the effective area of the MOSFET is significantly enhanced.
- The MFMIS-FET includes a MOSFET with a three-dimensional structure.
- The gate electrode of the MOSFET and the bottom electrode of the MFM are combined in some embodiments.
- The effective area of the MOSFET is increased without enlarging its footprint.
- The capacitance ratio between the MFM structure and the MOSFET is reduced.
- The drain current of the MOSFET is not compromised by the increased effective area.
Potential Applications: This technology could be applied in various semiconductor devices, particularly in power electronics, integrated circuits, and other electronic systems where MOSFETs are commonly used.
Problems Solved: The innovation addresses the challenge of increasing the effective area of a MOSFET without enlarging its footprint, which can lead to improved performance and efficiency in electronic devices.
Benefits: - Enhanced performance of MOSFETs - Increased efficiency in electronic systems - Reduced capacitance ratio - Improved power handling capabilities
Commercial Applications: This technology could have significant implications in industries such as telecommunications, automotive, consumer electronics, and renewable energy where power electronics play a crucial role.
Questions about MFMIS-FET: 1. How does the three-dimensional structure of the MOSFET contribute to increasing its effective area? 2. What are the specific advantages of uniting the gate electrode of the MOSFET and the bottom electrode of the MFM in terms of performance and efficiency?
Original Abstract Submitted
an mfmis-fet includes a mosfet having a three-dimensional structure that allows the mosfet to have an effective area that is greater than the footprint of the mfm or the mosfet. in some embodiment, the gate electrode of the mosfet and the bottom electrode of the mfm are united. in some, they have equal areas. in some embodiments, the mfm and the mosfet have nearly equal footprints. in some embodiments, the effective area of the mosfet is much greater than the effective area of the mfm. these structures reduce the capacitance ratio between the mfm structure and the mosfet without reducing the area of the mfm structure in a way that would decrease drain current.
