Taiwan semiconductor manufacturing company, ltd. (20240379745). INCREASING DEVICE DENSITY AND REDUCING CROSS-TALK SPACER STRUCTURES simplified abstract

INCREASING DEVICE DENSITY AND REDUCING CROSS-TALK SPACER STRUCTURES

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Huan-Chieh Su of Tianzhong Township (TW)

Chia-Hao Chang of Hsinchu City (TW)

Cheng-Chi Chuang of New Taipei City (TW)

Chih-Hao Wang of Baoshan Township (TW)

Yu-Ming Lin of Hsinchu City (TW)

INCREASING DEVICE DENSITY AND REDUCING CROSS-TALK SPACER STRUCTURES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240379745 titled 'INCREASING DEVICE DENSITY AND REDUCING CROSS-TALK SPACER STRUCTURES

The present disclosure pertains to an integrated chip with two transistors on a substrate. The first transistor has source/drain regions and a channel structure, while the second transistor also has source/drain regions and a channel structure. Both transistors have gate electrodes and air spacer structures.

• First transistor with source/drain regions and a channel structure
• Second transistor with source/drain regions and a channel structure
• Gate electrodes and air spacer structures for both transistors
• High-k dielectric spacer structure over low-k dielectric fin structure
• Separation of gate electrodes with dielectric spacer structure

Potential Applications: - Semiconductor industry for advanced integrated circuits - Electronics manufacturing for high-performance devices - Research and development in nanotechnology

Problems Solved: - Enhancing transistor performance - Improving chip density and efficiency - Reducing power consumption in electronic devices

Benefits: - Increased speed and efficiency of integrated circuits - Enhanced functionality of electronic devices - Potential for smaller and more powerful devices

Commercial Applications: Title: Advanced Integrated Chip Technology for High-Performance Electronics Description: This technology can be utilized in smartphones, computers, and other electronic devices to improve speed and efficiency, leading to better overall performance and user experience. The market implications include increased demand for high-performance chips in various industries.

Questions about Integrated Chip Technology: 1. How does the high-k dielectric spacer structure impact the performance of the transistors? 2. What are the potential challenges in manufacturing integrated chips with multiple transistors on a substrate?

Original Abstract Submitted

in some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. the first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. a first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. the second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. a second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. the integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.