Taiwan semiconductor manufacturing company, ltd. (20240379614). MULTI-LEVEL STACKING OF WAFERS AND CHIPS simplified abstract
Contents
- 1 MULTI-LEVEL STACKING OF WAFERS AND CHIPS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MULTI-LEVEL STACKING OF WAFERS AND CHIPS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Commercial Applications
- 1.9 Questions about the Technology
- 1.10 Original Abstract Submitted
MULTI-LEVEL STACKING OF WAFERS AND CHIPS
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Ming-Fa Chen of Taichung City (TW)
Cheng-Feng Chen of Zhubei City (TW)
Sung-Feng Yeh of Taipei City (TW)
Chuan-An Cheng of Zhubei City (TW)
MULTI-LEVEL STACKING OF WAFERS AND CHIPS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240379614 titled 'MULTI-LEVEL STACKING OF WAFERS AND CHIPS
Simplified Explanation
In this method, a wafer is bonded to a first carrier, with a semiconductor substrate and through-vias. Chips are bonded over the wafer with gaps in between, filled with gap-filling regions. A second carrier is then bonded onto the chips and gap-filling regions. The first carrier is removed, and electrical connectors are formed to connect to the chips through the through-vias.
- Semiconductor wafer bonded to carrier
- Chips bonded over wafer with gaps
- Gap-filling process to fill the gaps
- Second carrier bonded onto chips and gap-filling regions
- Electrical connectors formed to connect to chips through through-vias
Potential Applications
This technology can be used in the manufacturing of advanced semiconductor devices, such as microprocessors, memory chips, and sensors. It can also be applied in the production of high-density integrated circuits and electronic components.
Problems Solved
This method addresses the challenge of efficiently bonding chips onto a wafer with through-vias and filling the gaps between the chips. It streamlines the process of creating complex semiconductor devices with multiple components.
Benefits
- Improved efficiency in manufacturing semiconductor devices - Enhanced connectivity between chips and through-vias - Higher density of integrated circuits - Enhanced reliability of electronic components
Commercial Applications
The technology can be utilized in the semiconductor industry for the production of cutting-edge electronic devices. It can also find applications in the development of advanced sensors, communication devices, and computing systems.
Questions about the Technology
What are the potential commercial applications of this technology?
This technology can be applied in various industries, including semiconductor manufacturing, electronics, and telecommunications, to produce advanced devices with improved performance and reliability.
How does this method improve the efficiency of manufacturing semiconductor devices?
By streamlining the process of bonding chips onto a wafer with through-vias and filling the gaps between the chips, this method enhances the overall efficiency of creating complex semiconductor components.
Original Abstract Submitted
in a method, a wafer is bonded to a first carrier. the wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. the method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. the electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.
