Taiwan semiconductor manufacturing company, ltd. (20240379577). CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Shin-Puu Jeng of Hsinchu (TW)

Techi Wong of Zhubei City (TW)

Po-Yao Lin of Zhudong Township (TW)

Ming-Chih Yew of Hsinchu City (TW)

Po-Hao Tsai of Zhongli City (TW)

Po-Yao Chuang of Hsin-Chu (TW)

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240379577 titled 'CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Simplified Explanation: This patent application describes a method for creating a chip package structure, involving the formation of a conductive pillar, a recess, and a molding layer to house and connect a chip.

• Conductive pillar formed in substrate layer
• Recess created in substrate layer
• Chip placed in recess
• Molding layer formed around chip
• Redistribution structure formed over substrate layer to connect conductive pillar to chip

Key Features and Innovation:

• Innovative method for forming chip package structure
• Efficient and reliable connection between chip and conductive pillar
• Utilizes multiple layers for protection and connectivity

Potential Applications:

• Semiconductor industry
• Electronics manufacturing
• Integrated circuit packaging

Problems Solved:

• Ensures secure connection between chip and substrate
• Provides protection and support for the chip
• Facilitates efficient electrical connections

Benefits:

• Improved reliability of chip packaging
• Enhanced performance of electronic devices
• Simplified manufacturing process

Commercial Applications:

• Semiconductor companies
• Electronics manufacturers
• Technology companies

Prior Art: Research related to chip packaging methods and semiconductor manufacturing processes can provide insights into similar innovations in the field.

Frequently Updated Research: Ongoing research in semiconductor packaging technologies and materials could impact the development and implementation of this method.

Questions about Chip Package Structure: 1. How does this method compare to traditional chip packaging techniques? 2. What are the potential cost implications of implementing this innovative packaging method?

Original Abstract Submitted

a method for forming a chip package structure is provided. the method includes forming a conductive pillar in a substrate layer, forming a recess in the substrate layer, disposing a chip in the recess, forming a molding layer in the recess and surrounding the chip. and forming a redistribution structure over the substrate layer and electrically connecting the conductive pillar to the chip.