Taiwan semiconductor manufacturing company, ltd. (20240379149). COMPUTE IN MEMORY SYSTEM simplified abstract

COMPUTE IN MEMORY SYSTEM

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Mahmut Sinangil of Campbell CA (US)

COMPUTE IN MEMORY SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240379149 titled 'COMPUTE IN MEMORY SYSTEM

The abstract of the patent application describes a computing device that includes memory cells and an output interface with capacitors connected to read bit-lines, allowing for the generation of an analog output signal.

• Memory cells, such as 8-transistor SRAM cells, have isolated read bit-lines to prevent memory state upsets during simultaneous read activations.
• The output interface has capacitors with differing capacitance connected to read bit-lines, enabling the generation of an analog output signal weighted by the capacitor capacitance.
• The capacitors can share charge with each other to produce the analog output signal.
• The computing device is designed to charge or discharge the capacitors from the read bit-lines to generate the analog output signal.
• The method of making the computing device as described in the patent application is also disclosed.

Potential Applications: - This technology could be used in high-speed memory systems where analog output signals are required. - It may find applications in data processing systems that require precise analog output signals.

Problems Solved: - Prevents memory state upsets during simultaneous read activations. - Enables the generation of analog output signals weighted by capacitor capacitance.

Benefits: - Improved reliability and accuracy in memory systems. - Enhanced performance in data processing applications requiring analog output signals.

Commercial Applications: Potential commercial uses could include high-performance computing systems, data processing equipment, and memory-intensive applications.

Questions about the technology: 1. How does the use of capacitors with differing capacitance improve the generation of analog output signals? 2. What are the advantages of having isolated read bit-lines in memory cells for preventing memory state upsets?

Original Abstract Submitted

an example computing device includes an array of memory cells, such as 8-transistor sram cells, where the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. the computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. the output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, where the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. a method of making a computing device as described is also disclosed.