Samsung electronics co., ltd. (20240379635). 3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD FOR MANUFACTURING THE SAME simplified abstract
Contents
3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Organization Name
Inventor(s)
Choongbin Yim of Suwon-si (KR)
3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240379635 titled '3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
The abstract describes a three-dimensional integrated circuit structure with a redistribution structure, semiconductor dies, a substrate, molding material, and an interconnection structure.
- The structure includes a redistribution structure, first semiconductor die, substrate, molding material, and interconnection structure.
- The interconnection structure has first and second bonding pads directly bonded to each other.
- A second semiconductor die is placed on the interconnection structure.
Potential Applications:
- This technology can be used in advanced electronic devices such as smartphones, tablets, and computers.
- It can also be applied in automotive electronics, medical devices, and industrial equipment.
Problems Solved:
- Provides a compact and efficient way to integrate multiple semiconductor dies in a three-dimensional structure.
- Enhances the performance and functionality of electronic devices by improving interconnectivity.
Benefits:
- Increases the processing power and speed of electronic devices.
- Reduces the size and weight of devices while improving overall reliability.
Commercial Applications:
- This technology has significant commercial potential in the semiconductor industry for manufacturing high-performance electronic devices.
Questions about the technology: 1. How does the direct bonding of first and second bonding pads improve the overall efficiency of the integrated circuit structure? 2. What are the key advantages of using a three-dimensional structure in semiconductor integration?
Original Abstract Submitted
provided a three-dimensional (3d) integrated circuit structure including a redistribution structure, a first semiconductor die on the redistribution structure, a substrate on the redistribution structure and adjacent to the first semiconductor die, a molding material on the redistribution structure and between the first semiconductor die and the substrate, an interconnection structure on the substrate and the first semiconductor die, the interconnection structure including a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad of the second bonding pads being directly bonded to each first bonding pad of the first bonding pads, and a second semiconductor die on the interconnection structure.
