Samsung electronics co., ltd. (20240379622). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Joong Won Shin of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240379622 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract consists of a base chip with a top surface extending in two horizontal directions, a semiconductor chip stack with two chips stacked vertically on the base chip, and through vias and connection pads for electrical connections.
- The base chip has a top surface extending in two horizontal directions, intersecting each other.
- The semiconductor chip stack includes two chips stacked vertically on the base chip, aligned on respective sides.
- Through vias penetrate the base chip, first semiconductor chip, and second semiconductor chip, spaced apart in the horizontal direction.
- Connection pads on the base chip, first chip, and second chip make contact with the through vias for electrical connections.
Potential Applications: - This technology can be used in various electronic devices such as smartphones, tablets, and computers. - It can also be applied in automotive electronics, medical devices, and industrial equipment.
Problems Solved: - Provides a compact and efficient way to stack semiconductor chips for increased functionality in electronic devices. - Enables reliable electrical connections between stacked chips for seamless operation.
Benefits: - Reduces the overall size of electronic devices by stacking chips vertically. - Improves the performance and functionality of devices by integrating multiple chips in a compact package.
Commercial Applications: - The technology can be utilized by semiconductor manufacturers to produce advanced chip packages for consumer electronics and industrial applications. - It can also benefit companies developing cutting-edge electronic devices that require compact and high-performance semiconductor solutions.
Questions about the technology: 1. How does the vertical stacking of semiconductor chips improve the efficiency of electronic devices? 2. What are the key challenges in implementing through vias for electrical connections in semiconductor packages?
Original Abstract Submitted
a semiconductor package includes a base chip including a top surface extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, a semiconductor chip stack including a first semiconductor chip and a second semiconductor chip which are sequentially stacked on the base chip in a vertical direction and are aligned on respective sides in the vertical direction, first through vias penetrating the base chip and spaced apart from each other in the first horizontal direction, second through vias penetrating the first semiconductor chip and spaced apart from each other in the first horizontal direction, third through vias penetrating the second semiconductor chip and spaced apart from each other in the first horizontal direction, first connection pads contacting the first through vias, second connection pads contacting the second through vias, and third connection pads contacting the third through vias.
