Samsung electronics co., ltd. (20240379481). SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF CHIPS SEQUENTIALLY STACKED ON A PACKAGE SUBSTRATE BY AN ADHESIVE FILM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract
SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF CHIPS SEQUENTIALLY STACKED ON A PACKAGE SUBSTRATE BY AN ADHESIVE FILM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
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SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF CHIPS SEQUENTIALLY STACKED ON A PACKAGE SUBSTRATE BY AN ADHESIVE FILM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240379481 titled 'SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF CHIPS SEQUENTIALLY STACKED ON A PACKAGE SUBSTRATE BY AN ADHESIVE FILM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
The semiconductor package described in the patent application includes a package substrate with a receiving groove, a first semiconductor chip in the groove, a second semiconductor chip attached to the first chip without overlapping, an underfill member filling the groove, and a molding member covering the chips and underfill.
- Package substrate with receiving groove
- First semiconductor chip in the groove
- Second semiconductor chip attached to the first chip without overlapping
- Underfill member filling the groove with two cover portions
- Molding member covering the chips and underfill
Potential Applications: - Semiconductor packaging industry - Electronics manufacturing - Integrated circuit design
Problems Solved: - Efficient and secure attachment of multiple semiconductor chips - Protection of chips from external elements - Enhanced durability and reliability of semiconductor packages
Benefits: - Improved performance of semiconductor devices - Cost-effective packaging solution - Increased product lifespan
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Device Performance This technology can be utilized in various industries such as consumer electronics, automotive, telecommunications, and medical devices. It can lead to the development of more reliable and efficient electronic products, ultimately benefiting manufacturers and end-users.
Questions about Semiconductor Packaging Technology: 1. How does the underfill member contribute to the overall durability of the semiconductor package? The underfill member fills the gap between the chips and the substrate, providing structural support and protecting the chips from mechanical stress. 2. What are the potential challenges in implementing this advanced semiconductor packaging technology in mass production? The main challenges could include optimizing the manufacturing process, ensuring consistent quality control, and managing costs effectively.
Original Abstract Submitted
a semiconductor package includes: a package substrate having an upper surface and a receiving groove that has a predetermined depth from the upper surface; a first semiconductor chip disposed in the receiving groove; a second semiconductor chip attached to the first semiconductor chip, wherein the second semiconductor chip does not overlap a portion of the first semiconductor chip; an underfill member filling the receiving groove of the package substrate, wherein the underfill member includes a first cover portion and a second cover portion, wherein the first cover portion fills a gap between the first semiconductor chip and a bottom surface of the receiving groove, and the second cover portion covers the portion of the first semiconductor chip that is not overlapped by the second semiconductor chip; and a molding member covering the first semiconductor chip, the second semiconductor chip and the underfill member and disposed on the package substrate.
