Samsung electronics co., ltd. (20240379141). MEMORY DEVICE THAT INCLUDES A DUTY CORRECTION CIRCUIT, MEMORY CONTROLLER THAT INCLUDES A DUTY SENSING CIRCUIT, AND STORAGE DEVICE THAT INCLUDES A MEMORY DEVICE simplified abstract
MEMORY DEVICE THAT INCLUDES A DUTY CORRECTION CIRCUIT, MEMORY CONTROLLER THAT INCLUDES A DUTY SENSING CIRCUIT, AND STORAGE DEVICE THAT INCLUDES A MEMORY DEVICE
Organization Name
Inventor(s)
YOUNGMIN Jo of HWASEONG-SI (KR)
MANJAE Yang of HWASEONG-SI (KR)
BYUNGHOON Jeong of HWASEONG-SI (KR)
MEMORY DEVICE THAT INCLUDES A DUTY CORRECTION CIRCUIT, MEMORY CONTROLLER THAT INCLUDES A DUTY SENSING CIRCUIT, AND STORAGE DEVICE THAT INCLUDES A MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240379141 titled 'MEMORY DEVICE THAT INCLUDES A DUTY CORRECTION CIRCUIT, MEMORY CONTROLLER THAT INCLUDES A DUTY SENSING CIRCUIT, AND STORAGE DEVICE THAT INCLUDES A MEMORY DEVICE
Simplified Explanation: The patent application describes a storage device with multiple memory chips and a chip that adjusts clock signals based on comparison signals to improve performance.
- The storage device includes multiple memory chips and a chip.
- The memory chips generate signals based on clock signals.
- The chip receives and processes the signals to adjust clock signals for improved performance.
Key Features and Innovation:
- Utilizes multiple memory chips to generate signals based on clock signals.
- The chip adjusts clock signals based on comparison signals to optimize performance.
Potential Applications:
- Data storage devices
- Computer memory systems
- Electronic devices requiring efficient memory management
Problems Solved:
- Inefficient memory chip performance
- Lack of synchronization between clock signals and memory chip signals
Benefits:
- Improved memory chip performance
- Enhanced synchronization between clock signals and memory chip signals
Commercial Applications:
- Data centers
- Consumer electronics
- Industrial automation systems
Prior Art: Research related to memory chip synchronization and clock signal optimization in storage devices.
Frequently Updated Research: Ongoing studies on memory chip performance optimization and clock signal synchronization in storage devices.
Questions about Storage Device Technology: 1. How does the chip adjust clock signals based on comparison signals? 2. What are the potential drawbacks of using multiple memory chips in a storage device?
Original Abstract Submitted
a storage device includes a plurality of memory chips and a chip. the plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. the chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. the first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
