Intel corporation (20240355752). GLASS PACKAGE SUBSTRATE WITH CHIP DISAGGREGATION INTERFACE simplified abstract
Contents
GLASS PACKAGE SUBSTRATE WITH CHIP DISAGGREGATION INTERFACE
Organization Name
Inventor(s)
Telesphor Kamgaing of Chandler AZ (US)
GLASS PACKAGE SUBSTRATE WITH CHIP DISAGGREGATION INTERFACE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240355752 titled 'GLASS PACKAGE SUBSTRATE WITH CHIP DISAGGREGATION INTERFACE
The abstract of the patent application describes a package substrate with a glass layer core, a first routing layer on the first surface of the core, and a second routing layer on the second surface of the core with smaller traces.
- Glass layer core package substrate
- First routing layer with traces of a first width
- Second routing layer with traces of a second width smaller than the first width
Potential Applications: - Semiconductor packaging - Integrated circuits - Electronics manufacturing
Problems Solved: - Enhanced signal transmission - Improved reliability - Space-saving design
Benefits: - Higher performance - Increased durability - Cost-effective production
Commercial Applications: Title: Advanced Package Substrate Technology for Semiconductor Industry This technology can be utilized in the semiconductor industry for manufacturing high-performance electronic devices, leading to improved efficiency and reliability in various applications.
Questions about Package Substrate Technology: 1. How does the glass layer core enhance the performance of the package substrate? The glass layer core provides a stable and reliable base for the routing layers, ensuring efficient signal transmission and overall durability.
2. What are the advantages of having different widths of traces in the first and second routing layers? The variation in trace widths allows for optimized signal routing and space utilization, making the package substrate more efficient and compact.
Original Abstract Submitted
embodiments disclosed herein include a package substrate. in an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises a glass layer. in an embodiment, a first routing layer is over the first surface of the core, where the first routing layer comprises traces with a first width. in an embodiment, a second routing layer is over the second surface of the core, where the second routing layer comprises traces with a second width that is smaller than the first width.
