18062843. MEMORY DEVICE FOR OUTPUTTING TEST RESULTS simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
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MEMORY DEVICE FOR OUTPUTTING TEST RESULTS
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Inventor(s)
MEMORY DEVICE FOR OUTPUTTING TEST RESULTS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18062843 titled 'MEMORY DEVICE FOR OUTPUTTING TEST RESULTS
Simplified Explanation
The abstract describes a memory device that includes a memory cell array and a repair circuit. The repair circuit is designed to perform a repair operation and send a dirty signal to an external destination.
- The repair circuit selects a first redundancy address instead of a first fail address for a failed memory cell.
- It stores a mapping between the first fail address and the first redundancy address.
- If a second failed memory cell has the same fail address as the first one, the repair circuit ignores the previous mapping and outputs a dirty signal.
- The dirty signal causes a new mapping to be created, mapping the first fail address to a different redundancy address.
Potential applications of this technology:
- Memory devices in electronic devices such as computers, smartphones, and tablets.
- Data storage systems in servers and data centers.
- Embedded memory in various electronic devices.
Problems solved by this technology:
- Efficient repair of failed memory cells in a memory device.
- Reducing the impact of memory cell failures on the overall performance of the device.
- Minimizing the need for physical repairs or replacements of memory cells.
Benefits of this technology:
- Improved reliability and longevity of memory devices.
- Reduced downtime and maintenance costs.
- Enhanced performance and efficiency of electronic devices.
Original Abstract Submitted
A memory device includes a memory cell array and a repair circuit configured to perform a repair operation and output a dirty signal to an external destination external to the memory device. The repair circuit further performs selecting a first redundancy address of the redundancy memory cells instead of a first fail address of the first failed memory cell, storing a first redundancy mapping for the first fail address to the first redundancy address, and in response to determining a second fail address of a second failed memory cell matches the first fail address, ignoring the first redundancy mapping, and outputting a dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.
