18299174. LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR simplified abstract (Cisco Technology, Inc.)
Contents
LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR
Organization Name
Inventor(s)
Bibhu Prasad Das of Philadelphia PA (US)
Abhishek Bhat of Allentown PA (US)
Kadaba Lakshmikumar of Hillsborough NJ (US)
Romesh Kumar Nandwana of Chapel Hill NC (US)
LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18299174 titled 'LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR
Simplified Explanation: The patent application describes a charge-pump based low dropout (LDO) regulator that effectively addresses latch-up issues. This high power supply rejection (PSR) low noise LDO regulator utilizes a latch-up mitigated charge-pump voltage doubler with an NMOS pass transistor to provide a regulated output voltage with minimal noise for on-chip low jitter oscillators.
- The LDO regulator uses a latch-up mitigated charge-pump voltage doubler with an NMOS pass transistor.
- The architecture ensures high power supply rejection and low noise output voltage.
- Control circuitry and power supply timing sequence are employed to mitigate latch-up issues.
- Parasitic diodes associated with various transistors in the regulator are prevented from being forward biased.
- The innovation enables the provision of a very low-noise supply regulated output voltage with high power supply rejection for on-chip low jitter oscillators.
Potential Applications: 1. On-chip low jitter oscillators 2. Integrated circuits requiring low noise power supplies
Problems Solved: 1. Latch-up issues in LDO regulators 2. Noise in power supply outputs
Benefits: 1. High power supply rejection 2. Low noise output voltage 3. Mitigation of latch-up problems
Commercial Applications: The technology can be utilized in the development of high-performance integrated circuits, particularly in applications where low noise and high power supply rejection are critical, such as in communication systems and precision instrumentation.
Prior Art: Readers interested in exploring prior art related to this technology may start by researching latch-up mitigation techniques in LDO regulators and charge-pump voltage doublers.
Frequently Updated Research: Researchers are continually exploring advancements in latch-up mitigation techniques and noise reduction in power supply regulators, which may impact the development of similar technologies in the future.
Questions about LDO Regulators: 1. What are the key challenges in designing low noise LDO regulators? 2. How does the use of a charge-pump voltage doubler contribute to improving the performance of LDO regulators?
Original Abstract Submitted
A charge-pump based low dropout (LDO) regulator is provided that overcomes latch-up issues. The LDO regulator is a high PSR low noise LDO regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a N-type metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, pass transistor. This LDO regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. Latch-up is mitigated using control circuitry and a power supply timing sequence. This scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.
