18293858. INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD simplified abstract (Sony Group Corporation)
Contents
INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD
Organization Name
Inventor(s)
Yuuichi Nakamura of Tokyo (JP)
INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18293858 titled 'INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD
The patent application describes an information processing device with multiple CPUs, cache memories, and a main memory. Each CPU acquires a lock to access data exclusively in the main memory, with the lock ID associated with the CPU's access written in a cache line of the cache memories. When a CPU other than the one associated with the lock ID acquires the lock, the cache line is flushed.
- Multiple CPUs with associated cache memories and main memory
- CPUs acquire locks for exclusive data access in main memory
- Lock ID associated with CPU access written in cache line
- Cache line flushed when another CPU acquires the lock
- Efficient data access and management system
Potential Applications: - High-performance computing systems - Data processing centers - Server farms
Problems Solved: - Ensuring exclusive data access in multi-CPU systems - Preventing data corruption or loss due to concurrent access
Benefits: - Improved data access efficiency - Enhanced system reliability - Reduced risk of data conflicts
Commercial Applications: Title: "Advanced Data Access Management System for Multi-CPU Devices" This technology can be utilized in industries such as cloud computing, big data analytics, and high-frequency trading where fast and reliable data access is crucial.
Questions about the technology: 1. How does this technology improve data access efficiency in multi-CPU systems? 2. What are the potential drawbacks of flushing cache lines when a different CPU acquires the lock?
Original Abstract Submitted
An information processing device () includes a plurality of CPUs (), a plurality of cache memories () associated with the plurality of CPUs (), and a main memory (), each of the plurality of CPUs () acquires a lock for exclusively accessing data in the main memory (), and then accesses the data, data related to access of a corresponding CPU () and a lock ID for specifying the lock related to the access are associated and written in a cache line of each of the plurality of cache memories (), and a cache line of each of the plurality of cache memories () is flushed when a CPU () other than the corresponding CPU () acquires the lock specified based on the lock ID written in the cache line.
