18131956. METHOD OF FORMING A METAL LINER FOR INTERCONNECT STRUCTURES simplified abstract (Applied Materials, Inc.)

METHOD OF FORMING A METAL LINER FOR INTERCONNECT STRUCTURES

Organization Name

Applied Materials, Inc.

Inventor(s)

Jesus Candelario Mendoza-gutierrez of San Jose CA (US)

Aaron Dangerfield of San Jose CA (US)

Bhaskar Jyoti Bhuyan of San Jose CA (US)

Mark Saly of Santa Clara CA (US)

Yang Zhou of Milpitas CA (US)

Yong Jin Kim of Albany CA (US)

Carmen Leal Cervantes of Mountain View CA (US)

Ge Qu of Sunnyvale CA (US)

Zhiyuan Wu of San Jose CA (US)

Feng Chen of San Jose CA (US)

Kevin Kashefi of Santa Clara CA (US)

METHOD OF FORMING A METAL LINER FOR INTERCONNECT STRUCTURES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18131956 titled 'METHOD OF FORMING A METAL LINER FOR INTERCONNECT STRUCTURES

The abstract of the patent application describes methods of forming devices by depositing a dielectric layer on a substrate, with at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is selectively deposited on the bottom of the gap, followed by the formation of a barrier layer and the selective deposition of a metal liner on the barrier layer. The SAM is then removed after the metal liner is deposited.

• Selective deposition of a self-assembled monolayer (SAM) on the bottom of a gap in a dielectric layer on a substrate.
• Formation of a barrier layer on the SAM before depositing a metal liner.
• Removal of the SAM after the metal liner is selectively deposited.
• Use of specific chemical formulas for the SAM components.
• Application of the method to device fabrication processes.

Potential Applications: - Semiconductor device manufacturing - Microelectronics industry - Nanotechnology research

Problems Solved: - Improving the precision and control of metal deposition in device fabrication - Enhancing the performance and reliability of electronic devices

Benefits: - Increased efficiency in device manufacturing processes - Enhanced device performance and durability - Cost-effective fabrication methods

Commercial Applications: Title: Advanced Metal Deposition Method for Semiconductor Devices This technology could revolutionize the semiconductor industry by offering a more precise and efficient method for metal deposition in device fabrication processes. The improved control and reliability provided by this innovation could lead to the development of more advanced and reliable electronic devices, impacting various sectors such as consumer electronics, telecommunications, and automotive industries.

Questions about the technology: 1. How does the selective deposition of a self-assembled monolayer (SAM) improve metal deposition processes in device fabrication? 2. What are the specific benefits of using a barrier layer before depositing a metal liner in semiconductor device manufacturing?

Original Abstract Submitted

Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM has a general formula I to XIX, wherein R, R′, R, R, R, R, and Rare independently selected from hydrogen (H), alkyl, alkene, alkyne, and aryl, n is from 1 to 20, m is from 1 to 20, x is from 1 to 2, and y is from 1 to 2. A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.