18602321. Memory Circuitry And Methods Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)
Contents
Memory Circuitry And Methods Used In Forming Memory Circuitry
Organization Name
Inventor(s)
Shuangqiang Luo of Boise ID (US)
Indra V. Chary of Boise ID (US)
Kar Wui Thong of Boise ID (US)
Memory Circuitry And Methods Used In Forming Memory Circuitry - A simplified explanation of the abstract
This abstract first appeared for US patent application 18602321 titled 'Memory Circuitry And Methods Used In Forming Memory Circuitry
The memory circuitry described in the patent application consists of memory cells arranged in strings, with vertically-alternating insulative tiers and conductive tiers extending across different regions.
- Memory blocks are formed by these insulative and conductive tiers, with sub-blocks in their upper portions and sub-block trenches between adjacent sub-blocks.
- The memory cells in the strings pass through these memory blocks and sub-blocks, with trenches in different regions having varying widths at the top.
- The top of the sub-block trenches in the stair-step region is wider than those in the intermediate region, which are wider than those in the memory-array region.
Potential Applications: - This technology could be used in the development of high-density memory circuits for various electronic devices. - It may find applications in data storage systems, improving memory capacity and performance.
Problems Solved: - Addresses the need for more efficient memory circuitry with increased storage capacity. - Solves the challenge of optimizing memory cell arrangement for better performance.
Benefits: - Increased memory capacity and performance. - Enhanced efficiency in memory circuit design. - Potential cost savings in memory production processes.
Commercial Applications: Title: Advanced Memory Circuitry for High-Density Data Storage This technology could be utilized in the production of memory chips for smartphones, computers, and other electronic devices, enhancing their storage capabilities and overall performance. The market implications include improved data processing speeds and increased memory capacities, catering to the growing demand for higher storage capabilities in modern devices.
Questions about Memory Circuitry: 1. How does the design of the memory blocks and sub-block trenches contribute to the efficiency of the memory circuitry? 2. What are the potential challenges in implementing this technology in commercial memory chip production processes?
Original Abstract Submitted
Memory circuitry comprising strings of memory cells comprises vertically-alternating insulative tiers and conductive tiers that extend from a memory-array region into a stair-step region across an intermediate region that is between the memory-array region and the stair-step region. The insulative tiers and the conductive tiers comprise memory blocks upper portions of which individually comprise sub-blocks. Sub-block trenches are in the upper portions individually between immediately-laterally-adjacent of the sub-blocks. Strings of memory cells in the memory-array region comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks and in the sub-blocks. The sub-block trenches in the memory-array region, in the intermediate region, and in the stair-step region individually have a top. The top of individual of the sub-block trenches in the stair-step region has a narrowest-width that is larger than a narrowest-width of the top of the individual sub-block trenches in the intermediate region. The narrowest-width of the top of the individual sub-block trenches in the intermediate region is larger than a narrowest-width of the top of the individual sub-block trenches in the memory-array region. Other embodiments, including method, are disclosed.
