18624720. ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ERROR STATISTICS simplified abstract (Micron Technology, Inc.)
Contents
ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ERROR STATISTICS
Organization Name
Inventor(s)
Chun Sum Yeung of San Jose CA (US)
Pitamber Shukla of San Jose CA (US)
ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ERROR STATISTICS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18624720 titled 'ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ERROR STATISTICS
Simplified Explanation: The patent application discusses a memory sub-system that uses a block family error avoidance (BFEA) scan to adjust read voltages in a three-level cell (TLC) memory, which stores three bits per cell. The system compensates for variances in manufacturing and degradation over time that cause deviations in stored voltages from target voltages, reducing bit error rates.
Key Features and Innovation:
- Memory sub-system using BFEA scan to adjust read voltages in TLC memory
- Compensates for variances in manufacturing and degradation over time
- Reduces bit error rates by accurately adjusting read voltages
Potential Applications: This technology can be applied in various memory storage devices, such as solid-state drives, smartphones, and digital cameras.
Problems Solved: The technology addresses issues related to voltage deviations in memory cells, which can lead to erroneous results in read operations and increase the bit error rate.
Benefits:
- Improved accuracy of read voltages
- Reduced bit error rate
- Enhanced reliability of memory storage devices
Commercial Applications: Potential commercial applications include the manufacturing of high-performance solid-state drives, mobile devices with increased storage capacity, and improved digital cameras with reliable memory storage.
Prior Art: Researchers can explore prior patents related to memory sub-systems, error avoidance techniques, and voltage adjustment methods in memory devices.
Frequently Updated Research: Stay updated on advancements in memory technology, error correction methods, and voltage adjustment algorithms to enhance the performance of memory storage devices.
Questions about memory sub-system using BFEA scan to adjust read voltages: 1. How does the BFEA scan improve the accuracy of read voltages in TLC memory? 2. What are the potential implications of reducing bit error rates in memory storage devices?
Original Abstract Submitted
Aspects of the present disclosure are directed to a memory sub-system using a block family error avoidance (BFEA) scan to adjust read voltages. Three-level cell (TLC) memory stores three bits per cell. Due to variances in manufacturing and degradation over time, the actual voltages stored in the memory cells deviate from the target voltages. As a result, the comparisons between the read voltages and the stored voltages may generate erroneous results. A BFEA scan may be based on a single wordline and single page type. However, determining a single threshold voltage shift to apply to all read voltages may not compensate for all causes of voltage shifting. Accordingly, a BFEA scan may use multiple wordlines (e.g., one for each page) and determine different voltage offset values for each page. As a result, the accuracy of the read voltage applied is increased and the bit error rate (BER) is reduced.
