Cisco technology, inc. (20240348143). LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR simplified abstract
Contents
LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR
Organization Name
Inventor(s)
Bibhu Prasad Das of Philadelphia PA (US)
Abhishek Bhat of Allentown PA (US)
Kadaba Lakshmikumar of Hillsborough NJ (US)
Romesh Kumar Nandwana of Chapel Hill NC (US)
LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240348143 titled 'LATCH-UP MITIGATED CHARGE PUMP FOR HIGH POWER SUPPLY REJECTION LOW-DROPOUT REGULATOR
Simplified Explanation: The patent application describes a charge-pump based low dropout (LDO) regulator that addresses latch-up issues by using a high PSR low noise architecture with a latch-up mitigated charge-pump voltage doubler.
Key Features and Innovation:
- High PSR low noise LDO regulator design
- Latch-up mitigated charge-pump voltage doubler
- N-type metal-oxide-semiconductor field-effect transistor (MOSFET) pass transistor
- Control circuitry and power supply timing sequence to prevent forward biasing of parasitic diodes
Potential Applications: This technology can be used to provide a very low-noise supply regulated output voltage with high power supply rejection for on-chip low jitter oscillators.
Problems Solved: The technology addresses latch-up issues in LDO regulators, ensuring stable operation and preventing forward biasing of parasitic diodes.
Benefits:
- Improved stability and reliability of LDO regulators
- High power supply rejection for low noise applications
- Mitigation of latch-up issues for enhanced performance
Commercial Applications: Potential commercial applications include integrated circuits, communication devices, and other electronic systems requiring stable and low-noise power supplies.
Prior Art: Readers can explore prior research on latch-up mitigation in LDO regulators, charge-pump voltage doublers, and low noise power supply design.
Frequently Updated Research: Stay informed about the latest advancements in low noise power supply design, latch-up mitigation techniques, and integrated circuit technologies.
Questions about LDO Regulators: 1. How does the latch-up mitigated charge-pump voltage doubler improve the performance of LDO regulators? 2. What are the key considerations when designing a high PSR low noise LDO regulator?
Original Abstract Submitted
a charge-pump based low dropout (ldo) regulator is provided that overcomes latch-up issues. the ldo regulator is a high psr low noise ldo regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a n-type metal-oxide-semiconductor field-effect transistor (mosfet), nmos, pass transistor. this ldo regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. latch-up is mitigated using control circuitry and a power supply timing sequence. this scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.
