Sk hynix inc. (20240339147). MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF simplified abstract
Contents
MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF
Organization Name
Inventor(s)
Saeng Hwan Kim of Gyeonggi-do (KR)
MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240339147 titled 'MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF
The memory device described in the patent application includes a memory cell array with row-hammer cells that track accesses to rows, an address control circuit that generates consecutive refresh addresses, and a refresh control circuit that selectively initializes row-hammer cells while refreshing rows.
- Memory device with row-hammer cells to store accesses of rows
- Address control circuit generates first and second refresh addresses
- First refresh address indicates odd-numbered row during first cycle, even-numbered row during second cycle
- Refresh control circuit refreshes first and second rows corresponding to refresh addresses
- Selectively initializes row-hammer cells of first row during refresh
Potential Applications: - Improved memory performance in devices - Enhanced data retention and reliability in memory systems
Problems Solved: - Mitigating row-hammer effects in memory cells - Ensuring consistent and reliable data storage
Benefits: - Increased memory stability and longevity - Enhanced overall system performance - Reduced risk of data corruption or loss
Commercial Applications: Title: Advanced Memory Technology for Enhanced Data Storage This technology can be utilized in various commercial applications such as: - Consumer electronics - Data centers - Cloud computing servers
Questions about the technology: 1. How does the memory device prevent row-hammer effects? 2. What are the potential implications of this technology on the memory market?
Frequently Updated Research: Stay updated on the latest advancements in memory technology to leverage the benefits of this innovative memory device.
Original Abstract Submitted
a memory device includes a memory cell array including row-hammer cells configured to store a number of accesses of a corresponding row of a plurality of rows; an address control circuit configured to generate consecutive first and second refresh addresses according to a normal refresh command, wherein the first refresh address indicates an odd-numbered row during a first refresh cycle and an even-numbered row during a second refresh cycle; and a refresh control circuit configured to refresh, according to the normal refresh command, first and second rows respectively corresponding to the first and second refresh addresses and selectively initialize the row-hammer cells of the first row while refreshing the first row.
