Samsung electronics co., ltd. (20240347596). SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract
Contents
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Hyungjin Park of Suwon-si (KR)
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240347596 titled 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
The semiconductor device described in the abstract includes a substrate with an active pattern, first and second semiconductor patterns, a source/drain pattern, a gate electrode, and a gate insulating pattern.
- The first and second semiconductor patterns are vertically spaced apart on the active pattern.
- The source/drain pattern is connected to the first and second semiconductor patterns.
- The gate electrode is positioned between the first and second semiconductor patterns.
- The gate insulating pattern encloses the gate electrode and includes a high-k dielectric pattern, an inner spacer, and a mask insulating pattern.
- The inner spacer is located between the high-k dielectric pattern and the source/drain pattern.
- The mask insulating pattern has an etch selectivity with respect to the inner spacer.
Potential Applications: - This technology can be used in the manufacturing of advanced semiconductor devices. - It can improve the performance and efficiency of electronic devices.
Problems Solved: - Enhances the functionality and reliability of semiconductor devices. - Enables the production of smaller and more powerful electronic components.
Benefits: - Increased performance and efficiency of electronic devices. - Enhanced reliability and functionality of semiconductor devices.
Commercial Applications: - This technology can be applied in the production of smartphones, computers, and other electronic devices. - It has potential uses in the automotive industry for advanced driver assistance systems.
Questions about the technology: 1. How does the high-k dielectric pattern improve the performance of the semiconductor device? 2. What are the specific advantages of using the inner spacer in the gate insulating pattern?
Original Abstract Submitted
a semiconductor device including a substrate having an active pattern, first and second semiconductor patterns provided on the active pattern vertically spaced apart from each other, a source/drain pattern connected to the first and second semiconductor patterns, a gate electrode between the first and second semiconductor patterns, and a gate insulating pattern enclosing the gate electrode, wherein the gate insulating pattern includes, a high-k dielectric pattern enclosing the gate electrode, an inner spacer between the high-k dielectric pattern and the source/drain pattern, and a mask insulating pattern having an etch selectivity with respect to the inner spacer between the high-k dielectric pattern and the inner spacer.
