Intel corporation (20240347618). SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH IMPROVED CAP simplified abstract

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH IMPROVED CAP

Organization Name

intel corporation

Inventor(s)

Christine Radlinger of Portland OR (US)

Tongtawee Wacharasindhu of Hillsboro OR (US)

Andre Baran of Portland OR (US)

Kiran Chikkadi of Hillsboro OR (US)

Devin Merrill of McMinnville OR (US)

Nilesh Dendge of Hillsboro OR (US)

David J. Towner of Portland OR (US)

Christopher Kenyon of Portland OR (US)

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH IMPROVED CAP - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240347618 titled 'SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH IMPROVED CAP

The abstract describes self-aligned gate endcap (SAGE) architectures with improved caps and methods of fabricating them. In one example, an integrated circuit structure includes two gate structures over semiconductor fins with a gate endcap isolation structure between them. The isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall, with the cap layer having 70% or greater monoclinic crystallinity and containing hafnium and oxygen.

• Higher-k dielectric cap layer with improved caps
• Monoclinic crystallinity of 70% or greater
• Inclusion of hafnium and oxygen in the cap layer
• Self-aligned gate endcap (SAGE) architectures
• Fabrication methods for SAGE architectures

Potential Applications: - Advanced semiconductor devices - Integrated circuits - Nanoelectronics

Problems Solved: - Improved performance and efficiency of integrated circuits - Enhanced gate endcap isolation structures

Benefits: - Higher performance capabilities - Increased efficiency in semiconductor devices - Enhanced gate endcap isolation

Commercial Applications: Title: Advanced Semiconductor Devices with Improved Gate Endcap Isolation Structures This technology could be utilized in the production of advanced semiconductor devices, leading to improved performance and efficiency in integrated circuits. The market implications include increased demand for high-performance electronics and nanoelectronics.

Questions about SAGE Architectures: 1. How do SAGE architectures improve the performance of integrated circuits? SAGE architectures enhance the efficiency and performance of integrated circuits by providing improved gate endcap isolation structures with higher-k dielectric cap layers.

2. What are the key features of the fabrication methods for SAGE architectures? The fabrication methods for SAGE architectures involve the deposition of a higher-k dielectric cap layer with hafnium and oxygen on a lower-k dielectric wall, resulting in enhanced monoclinic crystallinity.

Original Abstract Submitted

self-aligned gate endcap (sage) architectures with improved caps, and methods of fabricating self-aligned gate endcap (sage) architectures with improved caps, are described. in an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. a second gate structure is over a second semiconductor fin. a gate endcap isolation structure is between the first gate structure and the second gate structure. the gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. the higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.