Intel corporation (20240347457). PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE simplified abstract

PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE

Organization Name

intel corporation

Inventor(s)

Andrew Collins of Chandler AZ (US)

Bharat P. Penmecha of Phoenix AZ (US)

Rajasekaran Swaminathan of Chandler AZ (US)

Ram Viswanath of Phoenix AZ (US)

PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240347457 titled 'PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE

The semiconductor package described in the abstract includes a first die with a first bridge interconnect region, a second die with a second bridge interconnect region, and a bridge die with contact areas to connect to the bridge interconnect regions.

• The first bridge interconnect region is larger than the second bridge interconnect region.
• Both bridge interconnect regions have multiple conductive bumps, with different average pitches between adjacent bumps.
• The average pitch between adjacent bumps in the first bridge interconnect region is larger than in the second bridge interconnect region.

Potential Applications: - This technology could be used in various semiconductor packaging applications where different die sizes and interconnect configurations are required.

Problems Solved: - Provides a solution for connecting different sized dies with varying interconnect configurations in a semiconductor package.

Benefits: - Allows for efficient and reliable connections between dies of different sizes within a semiconductor package. - Enables flexibility in designing semiconductor packages with diverse interconnect requirements.

Commercial Applications: - This technology could be valuable in the semiconductor industry for developing advanced packaging solutions for a wide range of electronic devices.

Questions about the technology: 1. How does the size difference between the first and second bridge interconnect regions impact the overall performance of the semiconductor package? 2. What are the potential challenges in manufacturing semiconductor packages with varying die sizes and interconnect configurations?

Original Abstract Submitted

various embodiments relate to a semiconductor package. the semiconductor package includes a first die. the first die includes a first bridge interconnect region. the semiconductor package further includes a second die. the second die includes a second bridge interconnect region. the semiconductor package includes a bridge die. the bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. in the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. an average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.