TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on October 10th, 2024
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on October 10th, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 70 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (23), H01L29/78 (14), H01L29/06 (14), H01L29/423 (13), H01L29/417 (10) H01L29/66795 (2), H01L29/78696 (2), G03F1/24 (2), H01L29/41733 (2), H01L27/0924 (2)
With keywords such as: layer, structure, semiconductor, conductive, gate, disposed, device, dielectric, substrate, and feature in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Ching Hsien LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Po TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen Liang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Szu LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi Chen HO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B25J15/06, B65G47/91
CPC Code(s): B25J15/0616
Abstract: embodiments of the present disclosure provide die pick and place tools with an improved vacuum tip that can perform attachment and detachment of an integrated circuit die without deforming dies. in one embodiment, a vacuum tip for transporting an integrated circuit die is provided. the vacuum tip includes a body having a top surface and a bottom surface, a plurality of grooves formed in the top surface and into the body, wherein the grooves extend radially outward from a center point of the body. the vacuum tip also includes a channel in the body, wherein the channel extends from a bottom of the grooves through the body to the bottom surface of the body, and the channel and the body are substantially co-axial.
Inventor(s): Chen-Yu LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/02, C23C14/02, C23C14/14, C23C14/56, C23C14/58, C23C16/06, C23C16/56, H01J37/32, H01L21/02, H01L29/40
CPC Code(s): C23C16/0245
Abstract: semiconductor processing apparatuses and methods are provided in which a pre-clean chamber receives a semiconductor wafer from a metal gate layer deposition chamber and at least partially removes an oxide layer on a metal gate layer. in some embodiments, a semiconductor processing apparatus includes a plurality of metal gate layer deposition chambers. each of the metal gate layer deposition chambers is configured to form a metal gate layer on a semiconductor wafer. at least one pre-clean chamber of the apparatus is configured to receive the semiconductor wafer from one of the metal gate layer deposition chamber and at least partially remove an oxide layer on the metal gate layer.
Inventor(s): Yu Min CHI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chieh LO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Lung HOU of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Jen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Su-Yu YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): F04D19/04, F04D29/58, H01L21/67
CPC Code(s): F04D19/042
Abstract: embodiments of the present disclosure provide a cryogenic pump for semiconductor processing, including a body having a flange, configured to be coupled to a process chamber, and an opening defined at a first end of the body; one or more capture plate modules disposed in the body; and a cold header thermally coupled to the one or more capture plate modules. a longitudinal axis of the body is defined from the first end of the body to a second end of the body. a first lateral dimension of the opening is less than a second lateral dimension of the body, the first and second lateral dimensions being defined perpendicular to the longitudinal axis. the second lateral dimension is defined at a position between the opening and the second end.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/43, G02B6/12, G02B6/42, H01S5/02326
CPC Code(s): G02B6/43
Abstract: a semiconductor package includes a first interposer having a first substrate, a first redistribution structure over a first side of the first substrate, and a first waveguide over the first redistribution structure and proximate to a first side of the first interposer, where the first redistribution structure is between the first substrate and the first waveguide. the semiconductor package further includes a photonic package attached to the first side of the first interposer, where the photonic package includes: an electronic die, and a photonic die having a plurality of dielectric layers and a second waveguide in one of the plurality of dielectric layers, where a first side of the photonic die is attached to the electronic die, and an opposing second side of the photonic die is attached to the first side of the first interposer, where the second waveguide is proximate to the second side of the photonic die.
Inventor(s): Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Huang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Wei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: a reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. the absorber layer includes one or more alternating pairs of a first cr based layer and a second cr based layer different from the first cr based layer.
Inventor(s): Hung-Yi TSAI of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Che HSIEH of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng LIEN of Cyonglin Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Hsun LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Ping CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Wei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Ping TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: a reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. the absorber layer includes a base material made of one or more of a cr based material, an ir based material, a pt based material, or co based material, and further contains one or more additional elements selected from the group consisting of si, b, ge, al, as, sb, te, se and bi.
Inventor(s): Yuan Chih LO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hui WENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han WU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/38, G03F7/004, H01L21/033, H01L29/66
CPC Code(s): G03F7/38
Abstract: a method of manufacturing a semiconductor device includes the following operations. a metal oxide photoresist layer is formed over a target layer. the metal oxide photoresist layer comprises a metal oxide core with organic ligands, a metal oxide framework with organic ligands, or a combination thereof. the metal oxide photoresist layer is exposed to an extreme ultraviolet radiation. the metal oxide photoresist layer is treated with a ligand leaving promoter. the metal oxide photoresist layer is developed to form a patterned photoresist. the target layer is etched by using the patterned photoresist as an etching mask.
Inventor(s): Eng Hock LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hao CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70316
Abstract: a lithography exposure system includes a light source, a substrate stage, and a mask stage between the light source and the substrate stage along an optical path from the light source to the substrate stage. the lithography exposure system further comprises a reflector along the optical path. the reflector comprises: a first layer having a first material and a first thickness; a second layer having the first material and a second thickness different from the first thickness; and a third layer between the first layer and the second layer, and having a second material different from the first material.
Inventor(s): Chien-Cheng CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Jen CHEN of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ming CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tran-Hui SHEN of Dounan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Cheng HO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shao HSU of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F1/36, G03F1/76, G03F1/78, G03F7/20, H01J37/317
CPC Code(s): G03F7/70441
Abstract: in a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. a pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. dummy pattern data for areas having pattern density less than a threshold density are generated. mask drawing data is generated from the circuit pattern data and the dummy pattern data. by using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. the drawn resist layer is developed using a developing solution. dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
Inventor(s): Bei-Shing LIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Lin LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F3/24, G05F1/565, G05F1/575, G05F3/26
CPC Code(s): G05F3/245
Abstract: an integrated circuit includes a first temperature-sensitive device configured to generate a first voltage, a second temperature-sensitive device configured to generate a second voltage, and an output terminal configured to generate a reference voltage which is a summation of the first voltage and the second voltage. the first voltage monotonically increases with an absolute temperature. the second voltage monotonically decreases with the absolute temperature. in the integrated circuit, a low-dropout regulator has a first input connected to the output terminal and an output connected to the gate of a power regulating transistor. the channel of the power regulating transistor is connected between a first terminal configured to receive a first supply voltage and a second terminal configured to generate a second supply voltage.
Inventor(s): Nozomu MATSUSHITA of Tokyo (JP) for taiwan semiconductor manufacturing company, ltd., Katsurou HAYASHI of Tokyo (JP) for taiwan semiconductor manufacturing company, ltd., Yasuko ANDOH of Tokyo (JP) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F3/04847, G06F3/04845
CPC Code(s): G06F3/04847
Abstract: some implementations described herein provide techniques and apparatuses for software parameter management through a universal interface. the techniques and apparatuses include a user device including a universal parameter management application. the user device may receive multiple sets of changeable parameters that may be provided to the user device using different formats, different machine languages, and/or different language scripts. the universal parameter management application may translate the multiple sets of changeable parameters into a common format, common machine language, and/or common language script. the user device may then provide each of the multiple sets through a common, changeable graphical representation of the changeable parameters on a graphical user interface of the device. the user may change each of the multiple sets of changeable parameters through an input that changes the common, changeable graphical representation.
Inventor(s): Kai-Yuan TING of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sandeep Kumar GOEL of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Chiang HUANG of Hsichu (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Han LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/39, G06N20/00
CPC Code(s): G06F30/39
Abstract: a non-transitory computer-readable storage medium is encoded with a set of instructions for designing a semiconductor device using electronic system level (esl) modeling for machine learning applications that, when executed by at least one processor, cause the at least one processor to: retrieve a source code operable to execute a plurality of operations of a machine learning algorithm; classify a first group of the plurality of operations as slow group operations and classify a second group of the plurality of operations as fast group operations, based on a time required to complete each operation; define a neural network operable to execute the slow group operations; define a trained neural network configuration including a plurality of interconnected neurons operable to execute the slow group operations; and generate an esl platform for evaluating a design of a semiconductor device based on the trained neural network configuration.
Inventor(s): Jen-Yuan CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jheng-Hong JIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chou LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Long Song LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/27, G06F115/02, G06F115/12, G06F119/18
CPC Code(s): G06F30/392
Abstract: the present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. the methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. an exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.
Inventor(s): Fu-An Tien of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Ting Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/394
CPC Code(s): G06F30/398
Abstract: systems and methods are provided for generating test patterns. in various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (drc) specified for a particular semiconductor manufacturing process or for particular types of devices. a test pattern generation system includes test pattern generation circuitry which receives a noise image. the test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. the test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.
Inventor(s): Sheng-Hsiung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hao CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chih OU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yao KU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Huan WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/3315, G06F30/337, G06F30/392, G06F30/396, G06F115/06, G06F119/06, G06F119/12
CPC Code(s): G06F30/398
Abstract: a multi-bit flip-flop includes a first flip-flop and a second flip-flop. the first flip-flop has a first driving capability. the first flip-flop includes a first set pin configured to receive a first set signal. the second flip-flop has a second driving capability different from the first driving capability. the second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. the first flip-flop and the second flip-flop are configured to share at least a first clock pin.
Inventor(s): Sanjeev Kumar Jain of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Atul Katoch of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/22, G11C7/10, G11C7/12, G11C8/08
CPC Code(s): G11C7/222
Abstract: devices, circuits, and methods are provided. a circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. the circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.
Inventor(s): Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Huang Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung Cho Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Wei Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chun You of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1675
Abstract: an exemplary magnetoresistive random-access memory (mram) cell is configured to store more than one bit. the mram cell includes a first magnetic tunneling junction (mtj) and a second mtj connected in parallel. the first mtj has a first diameter, the second mtj has a second diameter, and the second diameter is less than the first diameter. the mram cell further includes a transistor connected to the first mtj and the second mtj, a bit line connected to the first mtj and the second mtj, a word line connected to the transistor, and a source line connected to the transistor. a method of writing to the mram cell can include supplying one or more write voltages to the mram cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the mram cell.
Inventor(s): I-Che Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Ying Huang of Jhonghe City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0069
Abstract: a method includes setting a current level of a write signal to a first non-zero value for a first period of time. the write signal is provided to a memory element during the first period of time. the current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. the write signal is provided to the memory element during the second period of time. the current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. the write signal is provided to the memory element during the third period of time.
Inventor(s): Hiroki NOGUCHI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C29/42, G11C29/00, G11C29/20, G11C29/44
CPC Code(s): G11C29/42
Abstract: a memory system is provided. the memory system includes an error correction code circuit configured to correct a maximum of n error bits in each of multiple read data and a monitor circuit configured to monitor multiple fail word addresses associated with m error bits, and further configured to output a first word address in the fail word addresses to replace first memory locations corresponding to the first word address. each of the fail word addresses corresponds to one of multiple counter values, and the first word address corresponds to a maximum value of the counter values.
Inventor(s): Chi-Ming CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shiung TSAI of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yuan LI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L29/66, H01L29/778
CPC Code(s): H01L21/02617
Abstract: using surface activated bonding (sab) allows direct bonding of a silicon growth seed layer over an aluminum nitride substrate without an intervening oxide layer. the growth seed layer may include p− si(111) in order to allow for epitaxy of gallium nitride without exacerbating cte mismatch between silicon and the gallium nitride. as a result, defects in the gallium nitride are reduced, and bowing and cracking of the substrate is reduced, which improves performance of an electronic device including the gallium nitride. additionally, using sab is faster than other techniques for forming a growth seed layer as well as conserving power, processing resources, and raw materials that otherwise would have been expended in forming the growth seed layer.
Inventor(s): Fang-I Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Keng Tsai of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi Huang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/304, H01L21/67, H01L21/687
CPC Code(s): H01L21/304
Abstract: a method of trimming a wafer includes securing the wafer on a top surface of a wafer chuck of a wafer edge trimming apparatus, directing a water jet at an edge of the wafer to form a plurality of cracks at uniform intervals along the edge of the wafer, inserting a wedge of a removal module into a first crack of the plurality of cracks, and rotating the wafer, where during the rotation of the wafer, the wedge expands the first crack of the plurality of cracks and removes material from the edge of the wafer.
Inventor(s): Meng-Hsien Li of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Chuen Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yi Shen of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Li-Min Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsi Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Bin Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/306, C09K13/00, C23F1/00, C23F1/10, H01L21/308, H01L21/768
CPC Code(s): H01L21/30608
Abstract: a wet etching chemistry to selectively remove a polymer residue on an opening embedded in a low-k dielectric layer and an underlying stop layer in a process of forming an interconnect structure is provided. the wet etching chemistry includes: two type of organic solvents, wherein a concentration of the two type of organic solvents is greater than or equal to 70%; an alkali source amine, at least comprising a tertiary amine; an inhibitor; and water. in some embodiment, the wet etching chemistry is free of a peroxide to avoid damage to the wdc hard mask.
Inventor(s): Yao-Sheng HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Pi CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shen-Yang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin CHAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/311, H01L21/02, H01L29/66
CPC Code(s): H01L21/31116
Abstract: a method for manufacturing a semiconductor structure includes trimming a semiconductor region using a gaseous halogen-based etchant such that the trimmed semiconductor region has a first part and a second part which is formed on the first part and which has a halogen-terminated trimmed surface, and treating the halogen-terminated trimmed surface of the second part using a gaseous oxidant including hydrogen and oxygen such that the second part is oxidized to form an oxidized part, and such that the halogen-terminated trimmed surface is converted into a hydroxyl group-terminated surface of the oxidized part.
Inventor(s): Yan-Hong LIU of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chih WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Fu CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, G06T7/00, H01L21/677, H01L21/687, H04N25/71
CPC Code(s): H01L21/67288
Abstract: a workstation includes: a processing chamber configured to process a workpiece; a load port configured to interface with an environment external to the workstation; a robotic arm configured to transfer the workpiece between the load port and the processing chamber; and a defect sensor configured to detect a defect along a surface of the workpiece when transferred between the load port and the processing chamber.
Inventor(s): Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/68, B65G47/90, B65G47/91, H01L21/67, H01L21/683
CPC Code(s): H01L21/681
Abstract: a pick-and-place system is provided. the pick-and-place system includes: a wafer holder; a gantry over the wafer holder and comprising a stabilizer extending downwardly; a primary drive mechanism connected to the gantry and configured to drive the gantry; a secondary drive mechanism located at the gantry; and a suction head, wherein the secondary drive mechanism is connected to the suction head and configured to drive the suction head.
Inventor(s): Meng-Yu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang WU of Chubei (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei WU of Ju-Bei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu CHENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02
CPC Code(s): H01L21/76802
Abstract: the present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. the opening exposes the source/drain structure. the method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. the contact structure is in contact with the source/drain structure in the opening.
Inventor(s): Kuo-Chiang TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Hsiang SU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Jing YU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Huei CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L29/417, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L21/7682
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a gate electrode layer formed over a substrate, and a first insulating capping feature formed over the gate electrode layer. the semiconductor device structure includes a source/drain contact structure formed adjacent to the gate electrode layer and a second insulating capping feature formed over the source/drain contact structure. the second insulating capping feature and the first insulating capping feature are made of different materials, and an air gap directly below and in direct contact with the second insulating capping feature.
Inventor(s): Ko-Cheng Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Miao Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huiling Shang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/762, H01L27/092
CPC Code(s): H01L21/823878
Abstract: semiconductor structures and methods are provided. in an embodiment, a semiconductor structure includes a substrate including a first mesa structure and a second mesa structure, an isolation feature extending between the first mesa structure and the second mesa structure, a first vertical stack of nanostructures directly over the first mesa structure, first source/drain features coupled to the first vertical stack of nanostructures, a dielectric layer comprising a first portion disposed on the isolation feature and a second portion disposed between the first-type source/drain features and the substrate, and a first gate structure wrapping around each nanostructure of the first vertical stack of nanostructures.
Inventor(s): Wen-Shiang LIAO of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00
CPC Code(s): H01L23/3128
Abstract: a package structure and a formation method of a package structure are provided. the method includes surrounding a semiconductor chip with a protective layer. the protective layer has a first dielectric constant. the method also includes partially removing the protective layer to form an opening. the method further includes forming a dielectric structure partially or completely filling the opening. the dielectric structure has a second dielectric constant, and the second dielectric constant is higher than the first dielectric constant. the method further includes forming a redistribution structure over the semiconductor chip, the protective layer, and the dielectric structure.
Inventor(s): Chieh-Han Wu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsiung Tsai of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Chih Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ju Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/00, H01L23/532
CPC Code(s): H01L23/5226
Abstract: interconnect structures and methods of forming the same are provided. an interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
Inventor(s): Tai-I Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Lin Su of Taichung County (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Hsu Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Ping Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L21/8234, H01L23/522
CPC Code(s): H01L23/5283
Abstract: examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. in some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. a conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
Inventor(s): Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/498, H01L25/00, H01L25/065
CPC Code(s): H01L23/5383
Abstract: a semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. the first local interconnect component includes a first plurality of redistribution layers. the first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. the first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. the second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.
Inventor(s): Tsung-Fu Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/48, H01L23/498, H01L23/522, H01L25/00, H01L25/065
CPC Code(s): H01L23/5389
Abstract: a structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. the first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. the interposer includes a dielectric layer and through vias penetrating through the dielectric layer. the first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.
Inventor(s): Che Wei YANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ming WU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chau CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Yi HSIAO of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi YU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/08
Abstract: some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. a bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. as part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. the layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. the layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.
Inventor(s): Wei-Yu Chen of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wei Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Liang Chen of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/13
Abstract: embodiments provide a device structure and method of forming a device structure including an infill structure to capture solder materials within confines of openings of the infill structure. metal pillars of one device can penetrate through a non-conductive film and contact solder regions of another device. a separate underfill is not needed.
Inventor(s): Po-Yuan Teng of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Lung Pan of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Kuei Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tin-Hao Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Yang Lei of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Cheng Tseng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hui Lai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538
CPC Code(s): H01L24/24
Abstract: a package structure including at least one semiconductor die and a redistribution structure is provided. the semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. the redistribution structure includes signal lines and a pair of repair lines. the signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. the pair of repair lines is located above the pair of first signal lines and located right above the break. opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.
Inventor(s): Kuan-Yu Huang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Hui Huang of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Yun Hou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh Li of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/81
Abstract: a method of forming a semiconductor package includes: forming a first package component including a first and a second conductive bumps; forming a second package component including a third and a fourth conductive bumps, where dimensions of the first and second conductive bumps are less than dimensions of the third and fourth conductive bumps; and forming a first and a second joint structures to bond the second package component to the first package component. a first angle between an exposed sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the sidewall of the first conductive bump is less than a second angle between an exposed sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the sidewall of the second conductive bump.
Inventor(s): Yu-Ying Lai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chih Su of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ruey-Hsin Liu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L27/0255
Abstract: damage to an ldmos transistor from voltage overshoot in a power switching circuit operating at high switching speeds is prevented by embedding a diode under a drain region of the ldmos transistor. the embedded diode is doped more heavily than a drift region of the ldmos transistor and lowers a breakdown voltage of the ldmos transistor.
Inventor(s): Hung-Chih YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Mao CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01C7/00, H01C17/14, H01L21/8238, H01L27/01
CPC Code(s): H01L27/0629
Abstract: a semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.
Inventor(s): Chia-Hao Pao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/088
Abstract: a device includes a first and a second stacks of channel layers each extending from a first height to a second height. a first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. a second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. a gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. the fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.
Inventor(s): Wen-Ting LAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. the first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. the third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. the structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.
Inventor(s): Mao-Lin Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun Chu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/423, H01L29/49, H01L29/51, H01L29/786
CPC Code(s): H01L27/0924
Abstract: a semiconductor device according to an embodiment includes a first gate-all-around (gaa) transistor and a second gaa transistor. the first gaa transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. the second gaa transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. a first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. a third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.
Inventor(s): Chi-Hsien Chung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chi Hsiao of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Lin Yang of Kaohsiung city (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Han Liao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14607
Abstract: some embodiments relate to an ic device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.
Inventor(s): Hao-Lin Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14636
Abstract: some embodiments relate to an ic device, including a first chip; and a second chip bonded to the first chip at a bonding interface; where the first and second chips respectively comprise a first dielectric layer and a second dielectric layer directly contacting; the first chip further comprises a plurality of conductive pads recessed into the first dielectric layer and in a plurality of rows and columns; where the plurality of conductive pads are arranged with a zig-zag layout along the plurality of columns and along the plurality of rows and comprise a first conductive pad and a second conductive pad; the first chip further comprises a first shield line in the first dielectric layer and laterally between the first and second conductive pads, and the second chip further comprises a contact recessed into the second dielectric layer and directly contacting the first conductive pad at the bonding interface.
Inventor(s): Cheng-Wei Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin Liang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Kai Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung Chu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Shun Liao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ying Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/10, H01L29/417, H01L29/423, H01L29/66
CPC Code(s): H01L29/0665
Abstract: a semiconductor device with dual side source/drain (s/d) contact structures and methods of fabricating the same are disclosed. the semiconductor device includes first and second s/d regions, a nanostructured channel region disposed between the first and second s/d regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second s/d regions, a third contact structure disposed on a second surface of the first s/d region, and an etch stop layer disposed on a second surface of the second s/d region. the third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.
Inventor(s): Ming-Shuan Li of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Zi-Ang Su of Longtan Township (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Keung Leung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/423, H01L29/66, H01L29/73, H01L29/78
CPC Code(s): H01L29/41708
Abstract: embodiments include a first set of fins having an emitter of a bipolar junction transistor (bjt) disposed over the first set of fins, a second set of fins having a base of the bjt disposed over the second set of fins, and a third set of fins having a collector of the bjt disposed over the third set of fins. a first gate structure is disposed over the first set of fins adjacent to the emitter. a second gate structure is disposed over the second set of fins adjacent to the base. a third gate structure is disposed over the third set of fins adjacent to the collector. the first gate structure, second gate structure, and third gate structure are physically and electrically separated.
Inventor(s): Feng-Ching CHU of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/84, H01L27/12, H01L29/423, H01L29/45, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a stack of channel structures and a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. the semiconductor device structure also includes a gate stack wrapped around the channel structures and a backside conductive contact connected to the second epitaxial structure. the second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. the semiconductor device structure further includes an etch stop layer extending along a sidewall of the backside conductive contact and a bottom of the gate stack.
Inventor(s): Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L23/522, H01L23/528, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.
Inventor(s): Kuo-Chiang Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Huei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/311, H01L21/3213, H01L21/768, H01L23/522, H01L29/40
CPC Code(s): H01L29/41791
Abstract: an exemplary semiconductor device includes a substrate, a first conductive feature, a second conductive feature, and a third conductive feature over the substrate. the first conductive feature has a first top surface and a side surface. the third conductive feature is on the first top surface of the first conductive feature and is spaced away from the second conductive feature. the third conductive feature has a first sidewall and a second sidewall opposing the first sidewall. the first sidewall extends between the first conductive feature and the second conductive feature. at least a segment of the first sidewall has a first slope. the second sidewall has a second slope. the second slope is greater than the first slope.
Inventor(s): Chun Hsiung Tsai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kei-Wei CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/78
CPC Code(s): H01L29/66553
Abstract: a fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. the substrate has fins thereon. the insulators are located over the substrate and between the fins. the gate stack is located over the fins and over the insulators. the first spacer is located over the sidewall of the gate stack. the second spacer is located over the first spacer. the first spacer and the second spacer includes carbon. the third spacer is located between the first spacer and the second spacer.
Inventor(s): Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Huan Jao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/417, H01L29/78
CPC Code(s): H01L29/66795
Abstract: a method includes forming a fin protruding from a substrate; forming a gate structure extending over the fin; forming a source/drain region in the fin adjacent the gate structure; forming a first isolation region over the source/drain region; forming a first mask layer over the gate structure; etching the first isolation region using the first mask layer as an etch mask to form a first recess; conformally depositing a second mask layer over the first mask layer and within the first recess; depositing a third mask layer over the second mask layer; etching the third mask layer, the second mask layer, and the first isolation region to form a second recess that exposes the source./drain region; and depositing a conductive material in the second recess.
Inventor(s): Lung CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/8234, H01L29/08, H01L29/78
CPC Code(s): H01L29/66795
Abstract: the present disclosure describes a semiconductor structure and a method for forming the same. the method can include forming a recess structure in a substrate and forming a first semiconductor layer over the recess structure. the process of forming the first semiconductor layer can include doping first and second portions of the first semiconductor layer with a first n-type dopant having first and second doping concentrations, respectively. the second doping concentration can be greater than the first doping concentration. the method can further include forming a second semiconductor layer over the second portion of the first semiconductor layer. the process of forming the second semiconductor layer can include doping the second semiconductor layer with a second n-type dopant.
Inventor(s): Kuan-Ting Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Chuan You of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ruei Jhan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Yang Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/06
CPC Code(s): H01L29/6681
Abstract: a semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. the semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.
Inventor(s): Hsin-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yi CHENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wang YAO of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L21/8234, H01L27/088, H01L29/06, H01L29/423
CPC Code(s): H01L29/775
Abstract: an integrated circuit includes a first transistor and a second transistor. the first transistor includes first semiconductor channel layers, first gate structure, and a first source structure and a first drain structure on opposites sides of the first gate structure. the second transistor includes second semiconductor channel layers, second gate structure, and a second source structure and a second drain structure on opposites sides of the second gate structure. the first source structure of the first transistor is electrically coupled to the second drain structure of the second transistor. a thickness of each of the first semiconductor channel layers is less than a thickness of each of the second semiconductor channel layers, and a bandgap of a material of the first semiconductor channel layers is larger than a bandgap of a material of the second semiconductor channel layers.
Inventor(s): Guan-Lin Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chien Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/775
Abstract: a semiconductor device according to the present disclosure includes a first base fin and a second base fin extending from a substrate, an isolation feature disposed between the first base fin and the second base fin, a first dummy epitaxial layer disposed on the first base fin, a second dummy epitaxial layer disposed on the second base fin, a first insulator layer over the first dummy epitaxial layer, a second insulator layer over the second dummy epitaxial layer, a first source/drain feature disposed on the first insulator layer, a second source/drain feature disposed on the second insulator layer. a thickness of the first dummy epitaxial layer measured from a top surface of the first base fin is smaller than a thickness of the second dummy epitaxial layer measured from a top surface of the second base fin.
Inventor(s): Yuan-Cheng Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chi Wu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Jung Tu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/7817
Abstract: in some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. further, a shallow trench isolation (sti) structure is arranged within the substrate and between the source and drain regions. a gate electrode is arranged over the substrate, over the sti structure, and between the source and drain regions. a portion of the gate electrode extends into the sti structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the sti structure and a bottommost surface of the sti structure.
Inventor(s): Mark van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd., Martin Christopher Holland of Bertem (BE) for taiwan semiconductor manufacturing company, ltd., Matthias Passlack of Huldenberg (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/092, H01L29/06, H01L29/10, H01L29/16, H01L29/66, H10B12/00
CPC Code(s): H01L29/785
Abstract: a semiconductor device includes a fin protruding upwardly from a substrate. the fin includes a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls. the semiconductor device also includes a two-dimensional material layer disposed on the first and second sidewalls of the fin without being disposed on the top surface of the fin, and a gate stack disposed on the fin. the gate stack contacts a channel region defined in the two-dimensional material layer. the two-dimensional material layer includes a flat portion extending laterally away from the fin.
Inventor(s): Huei-Shan Wu of Keelung (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lii Huang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/768, H01L21/8234, H01L23/522, H01L27/088, H01L29/10, H01L29/417, H01L29/66
CPC Code(s): H01L29/7851
Abstract: a semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (esl) on the first conductive contact, and a second conductive contact extending through the esl. the first conductive contact has a first width. the second conductive contact has a second width, the second width being smaller than the first width. the esl overhangs a portion of the second conductive contact. a convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.
Inventor(s): Feng-Ching Chu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/3065, H01L21/3213, H01L21/762, H01L29/06, H01L29/10, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/7856
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. patterning the semiconductor material stack to form a trench. the patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. the first etch process and the second etch process are repeated a number of times. then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.
Inventor(s): Che-Lun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/285, H01L23/528, H01L29/06, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/78
CPC Code(s): H01L29/78618
Abstract: semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. in an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.
Inventor(s): Wei-Jen Lai of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yuan Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Yu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/08, H01L29/165, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/78696
Abstract: a semiconductor structure and a method of forming the same are provided. a semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.
Inventor(s): Cheng-Ting Chung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/78696
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (apt) layer disposed over the fin substrate, wherein the apt layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the apt layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (s/d) feature and a second epitaxial s/d feature disposed over the apt layer, wherein the gate structure is disposed between the first epitaxial s/d feature and the second epitaxial s/d feature; and an isolation layer disposed between the apt layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.
Inventor(s): Jiun-Yun LI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Nai-Wen HSU of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih HOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jui WU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen CHUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Yu LIU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/792, G11C16/04, G11C16/10, G11C16/14, G11C16/26, H01L29/15, H01L29/161
CPC Code(s): H01L29/792
Abstract: a flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. the semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. the semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. the semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. thea gate structure is over the second semiconductor channel layer. the source/drain regions are over the substrate and are on opposite sides of the gate structure.
Inventor(s): Yin-Kai Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming Hung of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Shin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Lin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sin-Yi Jiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L31/18, H01L27/146, H01L31/0288
CPC Code(s): H01L31/1804
Abstract: a method and structure providing an optical sensor having an optimized ge—si interface includes providing a substrate having a pixel region and a logic region. in some embodiments, the method further includes forming a trench within the pixel region. in various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. in some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. in some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.
Inventor(s): Chih-Chuan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hsiu HSU of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao PAO of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412, G11C11/417, H01L27/092
CPC Code(s): H10B10/12
Abstract: a four times contacted poly pitch (4cpp) static random-access memory (sram) cell layout is disclosed that forms six sram transistors from one od region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. for example, a vertical sram is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced ic technology nodes and improve memory performance. the vertical sram further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (m1) layer and/or a frontside m1 layer to minimize line capacitance and line resistance.
Inventor(s): Peng-Chun Liou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Yun Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ching Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/00
Abstract: a semiconductor device includes a conductive layer extending along a first lateral direction; a gate dielectric layer disposed over the conductive layer; a channel layer disposed over the gate dielectric layer and extending along a second lateral direction perpendicular to the first lateral direction; a first via-like structure, in direct contact with the channel layer, that is disposed along a first edge of the first channel extending along the second lateral direction; and a second via-like structure, in direct contact with the channel layer, that is disposed along a second, opposite edge of the first channel extending along the second lateral direction. the first via-like structure and second via-like structure are laterally separated apart along a third lateral direction that is clockwise tilted from the second lateral direction with a first positive angle.
Inventor(s): Ku-Feng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/00, G11C17/12
CPC Code(s): H10B20/50
Abstract: a read-only memory (rom) device includes a complementary field effect transistor (cfet) device which has a first semiconductor device of a first type, and a second semiconductor device of a second type different from the first type. the second semiconductor device is over or under the first semiconductor device. a first word line is electrically coupled to a gate of the first semiconductor device. a second word line is electrically coupled to a gate of the second semiconductor device. at least one bit line is electrically coupled to at least one of a first source/drain of the first semiconductor device, or a first source/drain of the second semiconductor device.
Inventor(s): Wei-Jen CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Jui TSOU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Yu LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Lin WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N52/80, H10B61/00, H10N52/00, H10N52/01
CPC Code(s): H10N52/80
Abstract: a memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an sot channel layer, and an mtj structure. the dielectric layer is over the substrate. the first ferromagnetic bottom electrode extends through the dielectric layer. the second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. the sot channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. the mtj structure is over the sot channel layer.
Inventor(s): Kuo-Pin Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Ju Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H10N70/00
CPC Code(s): H10N70/231
Abstract: a semiconductor device includes a first film, a second film, and a third film that each include a phase change material (pcm) and are arranged with respect to one another along a first lateral direction. the semiconductor device includes a first metal pad, a second metal pad, a third metal pad, and a fourth metal pad. the first and second metal pads are disposed over ends of the first film, respectively, the second and third metal pads are disposed over ends of the second film, respectively, and the third and fourth metal pads are disposed over ends of the third film, respectively. the semiconductor device includes a first heater, a second heater, and a third heater, respectively disposed below the first film, the second film, and the third film.
Inventor(s): Tsung-Hsueh Yang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00
CPC Code(s): H10N70/823
Abstract: a radio frequency (rf) switch includes a first conductive component and a second conductive component each disposed over a material layer in a cross-sectional side view. the rf switch includes a heater component disposed over the material layer in the cross-sectional side view. a segment of the heater component is disposed between the first conductive component and the second conductive component in the cross-sectional side view. an upper surface of the heater component is less elevated vertically than an upper surface of the first conductive component or the second conductive component in the cross-sectional side view. the rf switch includes a phase change material (pcm) disposed over the segment of the heater component and at least partially over the first conductive component and the second conductive component. a resistivity of the pcm changes in response to an application of heat. the heat is produced by the heater component.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on October 10th, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- B25J15/06
- B65G47/91
- CPC B25J15/0616
- Taiwan semiconductor manufacturing company, ltd.
- C23C16/02
- C23C14/02
- C23C14/14
- C23C14/56
- C23C14/58
- C23C16/06
- C23C16/56
- H01J37/32
- H01L21/02
- H01L29/40
- CPC C23C16/0245
- F04D19/04
- F04D29/58
- H01L21/67
- CPC F04D19/042
- G02B6/43
- G02B6/12
- G02B6/42
- H01S5/02326
- CPC G02B6/43
- G03F1/24
- CPC G03F1/24
- G03F7/38
- G03F7/004
- H01L21/033
- H01L29/66
- CPC G03F7/38
- G03F7/00
- CPC G03F7/70316
- G03F1/36
- G03F1/76
- G03F1/78
- G03F7/20
- H01J37/317
- CPC G03F7/70441
- G05F3/24
- G05F1/565
- G05F1/575
- G05F3/26
- CPC G05F3/245
- G06F3/04847
- G06F3/04845
- CPC G06F3/04847
- G06F30/39
- G06N20/00
- CPC G06F30/39
- G06F30/392
- G06F30/27
- G06F115/02
- G06F115/12
- G06F119/18
- CPC G06F30/392
- G06F30/398
- G06F30/394
- CPC G06F30/398
- G06F30/3315
- G06F30/337
- G06F30/396
- G06F115/06
- G06F119/06
- G06F119/12
- G11C7/22
- G11C7/10
- G11C7/12
- G11C8/08
- CPC G11C7/222
- G11C11/16
- CPC G11C11/1675
- G11C13/00
- CPC G11C13/0069
- G11C29/42
- G11C29/00
- G11C29/20
- G11C29/44
- CPC G11C29/42
- H01L29/778
- CPC H01L21/02617
- H01L21/304
- H01L21/687
- CPC H01L21/304
- H01L21/306
- C09K13/00
- C23F1/00
- C23F1/10
- H01L21/308
- H01L21/768
- CPC H01L21/30608
- H01L21/311
- CPC H01L21/31116
- G06T7/00
- H01L21/677
- H04N25/71
- CPC H01L21/67288
- H01L21/68
- B65G47/90
- H01L21/683
- CPC H01L21/681
- CPC H01L21/76802
- H01L29/417
- H01L29/49
- H01L29/78
- CPC H01L21/7682
- H01L21/8238
- H01L21/762
- H01L27/092
- CPC H01L21/823878
- H01L23/31
- H01L21/56
- H01L23/00
- CPC H01L23/3128
- H01L23/522
- H01L23/532
- CPC H01L23/5226
- H01L23/528
- H01L21/8234
- CPC H01L23/5283
- H01L23/538
- H01L21/48
- H01L23/498
- H01L25/00
- H01L25/065
- CPC H01L23/5383
- H01L23/48
- CPC H01L23/5389
- CPC H01L24/08
- CPC H01L24/13
- CPC H01L24/24
- CPC H01L24/81
- H01L27/02
- H01L29/06
- CPC H01L27/0255
- H01L27/06
- H01C7/00
- H01C17/14
- H01L27/01
- CPC H01L27/0629
- H01L27/088
- H01L29/423
- H01L29/786
- CPC H01L27/088
- CPC H01L27/0924
- H01L29/51
- H01L27/146
- CPC H01L27/14607
- CPC H01L27/14636
- H01L29/10
- CPC H01L29/0665
- H01L29/73
- CPC H01L29/41708
- H01L21/84
- H01L27/12
- H01L29/45
- CPC H01L29/41733
- H01L21/3213
- CPC H01L29/41791
- CPC H01L29/66553
- CPC H01L29/66795
- H01L29/08
- CPC H01L29/6681
- H01L29/775
- CPC H01L29/775
- CPC H01L29/7817
- H01L29/16
- H10B12/00
- CPC H01L29/785
- CPC H01L29/7851
- H01L21/3065
- CPC H01L29/7856
- H01L21/285
- CPC H01L29/78618
- H01L29/165
- CPC H01L29/78696
- H01L29/792
- G11C16/04
- G11C16/10
- G11C16/14
- G11C16/26
- H01L29/15
- H01L29/161
- CPC H01L29/792
- H01L31/18
- H01L31/0288
- CPC H01L31/1804
- H10B10/00
- G11C11/412
- G11C11/417
- CPC H10B10/12
- CPC H10B12/00
- H10B20/00
- G11C17/12
- CPC H10B20/50
- H10N52/80
- H10B61/00
- H10N52/00
- H10N52/01
- CPC H10N52/80
- H10N70/20
- H10N70/00
- CPC H10N70/231
- CPC H10N70/823
