Samsung electronics co., ltd. (20240339453). THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME simplified abstract
Contents
THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
Organization Name
Inventor(s)
Donghoon Hwang of Suwon-si (KR)
THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240339453 titled 'THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
The abstract describes a three-dimensional (3D) semiconductor device with various active regions and patterns on a substrate.
- Lower active region on the first surface of the substrate with lower channel and lower source/drain patterns.
- Upper active region on the lower active region with upper channel and upper source/drain patterns.
- Dam pattern vertically extending from lower to upper source/drain patterns.
- Lower active contact connected to the lower source/drain pattern.
- Upper active contact connected to the upper source/drain pattern.
- Vertical via along the dam pattern to connect the lower active contact to the upper active contact.
Potential Applications: - Advanced semiconductor technology - High-performance computing - Mobile devices - Internet of Things (IoT) devices
Problems Solved: - Enhanced electrical connectivity in 3D semiconductor devices - Improved performance and efficiency in electronic devices
Benefits: - Increased speed and reliability in electronic devices - Higher integration density - Reduced power consumption
Commercial Applications: - Semiconductor manufacturing industry - Electronics and consumer electronics sector - Research and development in semiconductor technology
Questions about the technology: 1. How does the vertical via improve electrical connectivity in the 3D semiconductor device? 2. What are the key advantages of having multiple active regions in the device architecture?
Original Abstract Submitted
a three-dimensional (3d) semiconductor device includes a substrate including a first surface and a second surface that are opposite to each other, a lower active region on the first surface of the substrate, the lower active region including a lower channel pattern and a lower source/drain pattern that are electrically connected to each other, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source/drain pattern that are electrically connected to each other, a dam pattern that vertically extends from the lower source/drain pattern to the upper source/drain pattern, a lower active contact electrically connected to the lower source/drain pattern, an upper active contact electrically connected to the upper source/drain pattern, and a vertical via that vertically extends along the dam pattern to electrically connect the lower active contact to the upper active contact.
