Samsung electronics co., ltd. (20240337687). METHODS AND SYSTEMS FOR VERIFYING INTEGRATED CIRCUITS simplified abstract
Contents
METHODS AND SYSTEMS FOR VERIFYING INTEGRATED CIRCUITS
Organization Name
Inventor(s)
Hyungjung Seo of Suwon-si (KR)
METHODS AND SYSTEMS FOR VERIFYING INTEGRATED CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240337687 titled 'METHODS AND SYSTEMS FOR VERIFYING INTEGRATED CIRCUITS
The abstract describes a system for verifying an integrated circuit by tracing a specified path for timing analysis among signal transfer paths within the circuit and generating design constraints and parasitic data for the path.
- Tracing module traces specified path for timing analysis within integrated circuit
- Generates list of nets in specified path based on netlist and path information
- Declares design constraints based on list of nets
- Generates parasitic data for nets in specified path
- Analysis module performs timing analysis based on design constraints and parasitic data
Potential Applications: - Verification of integrated circuits in semiconductor industry - Quality control in electronics manufacturing
Problems Solved: - Ensures accurate timing analysis for signal transfer paths - Helps identify and address potential design flaws in integrated circuits
Benefits: - Improves overall performance and reliability of integrated circuits - Reduces risk of timing issues and errors in circuit design
Commercial Applications: Title: "Integrated Circuit Verification System for Enhanced Performance" This technology can be used in semiconductor companies for efficient verification of integrated circuits, ensuring high-quality products and reducing time-to-market. It can also be valuable in the development of advanced electronic devices requiring precise timing analysis.
Prior Art: Researchers can explore existing patents related to integrated circuit verification systems, timing analysis tools, and netlist generation techniques to understand the evolution of this technology.
Frequently Updated Research: Researchers in the field of semiconductor design and verification continuously work on enhancing timing analysis algorithms, improving netlist generation processes, and optimizing design constraint declaration methods for integrated circuits.
Questions about Integrated Circuit Verification Systems: 1. How does this system contribute to the overall reliability of integrated circuits? - This system ensures accurate timing analysis and design constraint declaration, reducing the risk of errors in circuit design and improving performance. 2. What are the key factors to consider when implementing this technology in semiconductor manufacturing? - Factors such as netlist accuracy, path tracing efficiency, and timing analysis precision are crucial for successful integration of this system in semiconductor manufacturing processes.
Original Abstract Submitted
a system for verifying an integrated circuit includes a tracing module configured to: trace a specified path based on the specified path on which a timing analysis will be performed among a plurality of signal transfer paths within the integrated circuit and a netlist of the integrated circuit at a transistor level, generate a list of nets listing names of nets in the specified path based on the netlist and information on the specified path, declare design constraints for the specified path based on the list of the nets, and generate parasitic data for the net based on the list of the nets. the system further includes an analysis module configured to perform a timing analysis for the specified path based on the design constraints and the parasitic data.
