Samsung electronics co., ltd. (20240332255). SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME
Organization Name
Inventor(s)
HYUEKJAE Lee of Hwaseong-si (KR)
SO YOUN Lee of Hwaseong-si (KR)
JIHWAN Hwang of Hwaseong-si (KR)
JI-SEOK Hong of Yongin-si (KR)
SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240332255 titled 'SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME
The semiconductor package described in the patent application consists of a substrate, a first semiconductor chip, a second semiconductor chip, a first molding layer, and a second molding layer. The first semiconductor chip is positioned vertically between the second semiconductor chip and the substrate, with the first molding layer adjacent to the first semiconductor chip and the second molding layer adjacent to the second semiconductor chip.
- The first molding layer is made of a first molding material, while the second molding layer is made of a different second molding material.
- The top surface of the first semiconductor chip and the first molding layer are flat and coplanar with each other.
- The ratio of the difference in coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the second molding layer and the substrate is between 5:1 and 20:1.
Potential Applications: - This technology can be used in the manufacturing of advanced semiconductor packages for various electronic devices. - It can improve the thermal performance and reliability of semiconductor chips in high-performance applications.
Problems Solved: - Addresses issues related to thermal expansion and reliability in semiconductor packaging. - Provides a solution for vertically stacking semiconductor chips while maintaining structural integrity.
Benefits: - Enhanced thermal performance and reliability of semiconductor packages. - Allows for more compact and efficient electronic devices.
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Performance This technology can be applied in the production of smartphones, tablets, laptops, and other consumer electronics where space-saving and thermal management are crucial factors.
Prior Art: Readers can explore prior art related to semiconductor packaging technologies, vertical chip stacking, and materials with different coefficients of thermal expansion.
Frequently Updated Research: Researchers are constantly exploring new materials and techniques to further improve the thermal performance and reliability of semiconductor packages.
Questions about Semiconductor Packaging Technology: 1. How does the use of different molding materials in the first and second molding layers impact the overall performance of the semiconductor package? 2. What are the potential challenges in manufacturing semiconductor packages with vertically stacked chips using this technology?
Original Abstract Submitted
a semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. the second molding layer is formed of a second molding material different from the first molding material. a top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.
