Intel corporation (20240333471). SIDE-CHANNEL RESISTANT MULTIPLICATIVELY MASKED AES ENGINE WITH ZERO-VALUE ATTACK DETECTION simplified abstract
Contents
SIDE-CHANNEL RESISTANT MULTIPLICATIVELY MASKED AES ENGINE WITH ZERO-VALUE ATTACK DETECTION
Organization Name
Inventor(s)
Raghavan Kumar of Hillsboro OR (US)
Sanu Mathew of Portland OR (US)
Sachin Taneja of Hillsboro OR (US)
SIDE-CHANNEL RESISTANT MULTIPLICATIVELY MASKED AES ENGINE WITH ZERO-VALUE ATTACK DETECTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240333471 titled 'SIDE-CHANNEL RESISTANT MULTIPLICATIVELY MASKED AES ENGINE WITH ZERO-VALUE ATTACK DETECTION
The abstract of this patent application describes a method involving cryptographic operations on masked inputs to enhance security.
- Combining a round key with masked plaintext in a first adder circuit to generate an additively masked input.
- Converting the additively masked input to a multiplicatively masked input in a first converter.
- Performing a non-linear inverse operation on the multiplicatively masked input in a substitution box circuit, depending on whether the input is zero or non-zero.
Potential Applications: - Secure communication systems - Data encryption and decryption - Secure storage of sensitive information
Problems Solved: - Enhancing security in cryptographic operations - Preventing unauthorized access to encrypted data
Benefits: - Improved data security - Protection against cryptographic attacks - Enhanced privacy for sensitive information
Commercial Applications: Cryptocurrency transactions, secure messaging applications, secure cloud storage services
Questions about the technology: 1. How does this method improve the security of cryptographic operations? 2. What are the potential implications of using masked inputs in cryptographic algorithms?
Frequently Updated Research: Stay updated on advancements in cryptographic techniques and algorithms to enhance data security.
Original Abstract Submitted
in one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. other embodiments are described and claimed.
