Intel corporation (20240332399). GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION simplified abstract

GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Organization Name

intel corporation

Inventor(s)

Tahir Ghani of Portland OR (US)

Byron Ho of Hillsboro OR (US)

Michael L. Hattendorf of Portland OR (US)

Christopher P. Auth of Portland OR (US)

GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240332399 titled 'GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

The patent application is related to the fabrication of advanced integrated circuit structures, specifically focusing on the 10 nanometer node and smaller structures. The method involves forming fins and gate structures over the fins, with a dielectric material structure between the gate structures. Portions of the gate structures are removed to expose different portions of the fins, with one portion of the fins being removed while the other portion remains intact.

• Formation of fins and gate structures in advanced integrated circuit fabrication
• Use of dielectric material structure between gate structures
• Selective removal of portions of gate structures to expose different parts of fins
• Removal of one portion of exposed fins while leaving the other portion intact
• Focus on 10 nanometer node and smaller integrated circuit structures

Potential Applications: - Semiconductor manufacturing - Electronics industry - Nanotechnology research

Problems Solved: - Enhancing the performance and efficiency of integrated circuits - Achieving smaller node sizes in circuit fabrication - Improving the functionality of electronic devices

Benefits: - Increased processing power in electronic devices - Reduction in size and energy consumption of integrated circuits - Advancement in semiconductor technology

Commercial Applications: Title: "Innovative Integrated Circuit Fabrication for Enhanced Performance" This technology can be utilized in the production of high-performance electronic devices such as smartphones, computers, and IoT devices. It can also benefit companies involved in semiconductor manufacturing and research.

Questions about the technology: 1. How does the selective removal of portions of gate structures impact the overall performance of the integrated circuit? 2. What are the potential challenges in scaling down the node size to 10 nanometers and smaller in integrated circuit fabrication?

Original Abstract Submitted

embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. a dielectric material structure is formed between adjacent ones of the plurality of gate structures. a portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. the exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.