Intel corporation (20240332389). PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON DEVICES simplified abstract
Contents
PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON DEVICES
Organization Name
Inventor(s)
Nicole Thomas of Portland OR (US)
Michael K. Harper of Hillsboro OR (US)
Leonard P. Guler of Hillsboro OR (US)
Marko Radosavljevic of Portland OR (US)
Thoe Michaelos of Portland OR (US)
PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240332389 titled 'PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON DEVICES
The semiconductor device described in the abstract consists of stacked semiconductor channels with a gate dielectric surrounding them.
- The device includes first and second semiconductor channels with a spacing between them.
- Individual semiconductor channels are surrounded by a gate dielectric.
- First workfunction metal surrounds the first semiconductor channels, while second workfunction metal surrounds the second semiconductor channels.
Potential Applications: - This technology can be used in the development of advanced semiconductor devices for various electronic applications. - It can enhance the performance and efficiency of integrated circuits in electronic devices.
Problems Solved: - Addresses the need for improved semiconductor devices with enhanced functionality and performance. - Solves challenges related to the integration of different semiconductor materials in a single device.
Benefits: - Improved performance and efficiency of semiconductor devices. - Enhanced functionality and versatility in electronic applications.
Commercial Applications: - This technology has potential commercial applications in the semiconductor industry for the development of advanced electronic devices. - It can be utilized in the production of high-performance integrated circuits for consumer electronics, telecommunications, and computing devices.
Prior Art: - Researchers and developers can explore prior art related to stacked semiconductor channels, gate dielectrics, and workfunction metals in semiconductor devices.
Frequently Updated Research: - Stay updated on the latest research and advancements in semiconductor technology, particularly in the development of stacked semiconductor channels and gate dielectrics.
Questions about the technology: 1. How does the use of different workfunction metals impact the performance of the semiconductor device? 2. What are the potential challenges in manufacturing semiconductor devices with stacked semiconductor channels and gate dielectrics?
Original Abstract Submitted
embodiments disclosed herein include semiconductor devices and methods of making such devices. in an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. in an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. the semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. in an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
