Intel corporation (20240330210). METHOD AND APPARATUS TO IMPROVE PERFORMANCE AND BATTERY LIFE FOR SYSTEMS WITH DISCRETE UNIVERSAL SERIAL BUS CONNECTOR simplified abstract

METHOD AND APPARATUS TO IMPROVE PERFORMANCE AND BATTERY LIFE FOR SYSTEMS WITH DISCRETE UNIVERSAL SERIAL BUS CONNECTOR

Organization Name

intel corporation

Inventor(s)

Ravishankar Subramanian of Bangalore (IN)

Venkataramani Gopalakrishnan of Folsom CA (US)

Yaniv Hayat of Herzliya (IL)

Reuven Rozic of Binyamina (IL)

METHOD AND APPARATUS TO IMPROVE PERFORMANCE AND BATTERY LIFE FOR SYSTEMS WITH DISCRETE UNIVERSAL SERIAL BUS CONNECTOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240330210 titled 'METHOD AND APPARATUS TO IMPROVE PERFORMANCE AND BATTERY LIFE FOR SYSTEMS WITH DISCRETE UNIVERSAL SERIAL BUS CONNECTOR

The patent application relates to reducing power consumption in a serial link, such as a PCIe link, between a system-on-a-chip (SoC) and a USB4 host in a computing device.

• The link connects to adapters in a USB4 router, including USB3, PCIe, host interface, and DisplayPort adapters.
• Bandwidth of the link can be adjusted based on measured data rate, optimizing power consumption.
• Data rate is determined by downstream transmissions from the SoC to the USB4 host.
• Transmitter clock rate can be adjusted to modify bandwidth and reduce power usage.

1. 1. 1. Potential Applications:

This technology can be applied in various computing devices to improve power efficiency and optimize data transfer speeds.

1. 1. 1. Problems Solved:

This innovation addresses the issue of excessive power consumption in serial links, providing a solution to optimize bandwidth based on data rate.

1. 1. 1. Benefits:

- Reduced power consumption - Improved efficiency in data transfer - Enhanced performance in computing devices

1. 1. 1. Commercial Applications:

Optimizing power consumption in serial links can benefit manufacturers of laptops, tablets, smartphones, and other computing devices by extending battery life and improving overall performance.

1. 1. 1. Prior Art:

Readers can explore prior research on power optimization in serial links, PCIe technology, and USB4 connectivity to gain a deeper understanding of the innovation.

1. 1. 1. Frequently Updated Research:

Stay updated on advancements in power efficiency in serial links, PCIe technology, and USB4 connectivity to leverage the latest developments in the field.

1. 1. 1. 1. Questions about Power Optimization in Serial Links:

1. How does adjusting the transmitter clock rate impact power consumption in a serial link? 2. What are the potential implications of optimizing bandwidth based on data rate in computing devices?

Original Abstract Submitted

embodiments herein relate to reducing the power consumption of a serial link such as peripheral component interconnect express (pcie) link. the link may extend between a system-on-a-chip (soc) or other circuit and a universal serial bus (usb4) host in a computing device. the usb4 host includes a pcie switch which connects lanes of the link to adapters in a usb4 router, such as a usb3 adapter, a pcie adapter, a host interface adapter and a displayport adapter. the available bandwidth of the link can be adjusted based on a measured data rate. for example, the data rate can be compared to one or more thresholds. in one approach, the data rate is based on downstream transmissions, from the soc to the usb4 host. a transmitter clock rate can be adjusted to adjust the bandwidth and reduce power consumption.