Intel corporation (20240330000). CIRCUITRY AND METHODS FOR IMPLEMENTING FORWARD-EDGE CONTROL-FLOW INTEGRITY (FECFI) USING ONE OR MORE CAPABILITY-BASED INSTRUCTIONS simplified abstract
CIRCUITRY AND METHODS FOR IMPLEMENTING FORWARD-EDGE CONTROL-FLOW INTEGRITY (FECFI) USING ONE OR MORE CAPABILITY-BASED INSTRUCTIONS
Organization Name
Inventor(s)
Scott D. Constable of Portland OR (US)
Michael Lemay of Hillsboro OR (US)
CIRCUITRY AND METHODS FOR IMPLEMENTING FORWARD-EDGE CONTROL-FLOW INTEGRITY (FECFI) USING ONE OR MORE CAPABILITY-BASED INSTRUCTIONS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240330000 titled 'CIRCUITRY AND METHODS FOR IMPLEMENTING FORWARD-EDGE CONTROL-FLOW INTEGRITY (FECFI) USING ONE OR MORE CAPABILITY-BASED INSTRUCTIONS
Simplified Explanation: The patent application describes techniques for implementing forward-edge control-flow integrity (FECFI) using capability instructions in a hardware processor. This involves a capability management circuit in the processor to check memory access requests based on capabilities, which include address and bounds fields. A decoder circuit decodes instructions, including capabilities for function calls, to ensure secure execution.
Key Features and Innovation:
- Implementation of forward-edge control-flow integrity (FECFI) using capability instructions in a hardware processor.
- Capability management circuit for checking memory access requests based on capabilities with address and bounds fields.
- Decoder circuit to decode instructions, including capabilities for function calls, ensuring secure execution.
Potential Applications: The technology can be applied in secure computing environments, such as in critical infrastructure systems, financial institutions, and cloud computing platforms.
Problems Solved: The technology addresses security vulnerabilities related to control-flow integrity in hardware processors, enhancing system security and preventing unauthorized access to memory.
Benefits:
- Improved security in hardware processors.
- Prevention of unauthorized access to memory.
- Enhanced control-flow integrity for secure computing environments.
Commercial Applications: The technology can be utilized in industries requiring high levels of security, such as defense, finance, and data centers, to protect sensitive information and prevent cyber attacks.
Prior Art: Readers can explore prior research on control-flow integrity, hardware security, and capability-based systems to understand the background of this technology.
Frequently Updated Research: Stay updated on advancements in hardware security, control-flow integrity techniques, and capability-based systems to enhance understanding and implementation of this technology.
Questions about Forward-Edge Control-Flow Integrity Using Capability Instructions: 1. What are the key benefits of implementing forward-edge control-flow integrity using capability instructions in a hardware processor? 2. How does the capability management circuit in the hardware processor enhance system security and prevent unauthorized access to memory?
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Original Abstract Submitted
techniques for implementing forward-edge control-flow integrity (fecfi) using capability instructions in a hardware processor are described. in certain examples, a hardware processor (e.g., core) includes a capability management circuit to check a capability for a memory access request for a memory, the capability comprising an address field and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising: a first capability to indicate a first call table comprising a respective entry for each of a plurality of functions of a first type, a field to indicate a first offset of a first entry for a first function requested for execution, and an opcode to indicate the capability management circuit is to perform a first check that the first offset is within a lower bound and an upper bound of the first capability and a second check that the first offset is a permitted offset for the entries in the first call table, and in response to the first check and the second check both passing, cause an execution circuit to execute the first function; and the execution circuit to execute the decoded single instruction according to the opcode.
