Intel corporation (20240329129). TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE simplified abstract
Contents
TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE
Organization Name
Inventor(s)
Sridhar Muthrasanallur of Bengaluru (IN)
Debendra Das Sharma of Saratoga CA (US)
Swadesh Choudhary of Mountain View CA (US)
Gerald Pasdast of San Jose CA (US)
Peter Onufryk of Flanders NJ (US)
TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240329129 titled 'TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE
Simplified Explanation: The patent application discusses technologies for a unified debug and test architecture in chiplets, which are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, allowing for common debugging protocols to be used across different chiplets.
- Chiplets integrated on an integrated circuit package
- Connected by a package interconnect like UCIE
- Each chiplet has debug nodes connected by an on-chiplet network
- Package debug endpoint acts as a link endpoint for off-package links like PCIe
- Debug messages can be sent to the package debug endpoint over a PCIe link
- Debug functionality at each node can be probed using a common protocol
Potential Applications: 1. Semiconductor industry for integrated circuit packages 2. Debugging and testing of chiplets from different vendors 3. Improving efficiency and reliability of integrated circuits
Problems Solved: 1. Standardizing debug and test protocols across chiplets 2. Facilitating integration of chiplets from different vendors 3. Enhancing the reliability of integrated circuits
Benefits: 1. Streamlined debugging and testing processes 2. Compatibility with chiplets from various sources 3. Improved overall performance and reliability of integrated circuits
Commercial Applications: Unified Debug and Test Architecture in Chiplets: Enhancing Efficiency and Reliability in Integrated Circuits
Questions about Unified Debug and Test Architecture in Chiplets: 1. How does the use of a common protocol benefit the integration of chiplets from different vendors? 2. What are the potential challenges in implementing this unified debug and test architecture in chiplets?
Original Abstract Submitted
technologies for a unified debug and test architecture in chiplets is disclosed. in an illustrative embodiment, several chiplets are integrated on an integrated circuit package. the chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (ucie) interconnect. each chiplet includes several debug nodes, which are connected by an on-chiplet network. one of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (pcie) link. in use, debug messages can be sent to the package debug endpoint over a pcie link. the debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. in this manner, chiplets from different vendors can be integrated into the same package and tested using common software.
