Intel corporation (20240329114). DEVICE UNDER TEST (DUT) STRUCTURES IN FILL REGIONS OF PRODUCT DIE FOR VOLTAGE CONTRAST (VC) DEFECT DETECTION FOR IMPROVED YIELD LEARNING simplified abstract
DEVICE UNDER TEST (DUT) STRUCTURES IN FILL REGIONS OF PRODUCT DIE FOR VOLTAGE CONTRAST (VC) DEFECT DETECTION FOR IMPROVED YIELD LEARNING
Organization Name
Inventor(s)
Sairam Subramanian of Portland OR (US)
Amit Paliwal of Hillsboro OR (US)
Dipto Thakurta of Portland OR (US)
Manish Sharma of Portland OR (US)
Daniel Murray of Portland OR (US)
DEVICE UNDER TEST (DUT) STRUCTURES IN FILL REGIONS OF PRODUCT DIE FOR VOLTAGE CONTRAST (VC) DEFECT DETECTION FOR IMPROVED YIELD LEARNING - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240329114 titled 'DEVICE UNDER TEST (DUT) STRUCTURES IN FILL REGIONS OF PRODUCT DIE FOR VOLTAGE CONTRAST (VC) DEFECT DETECTION FOR IMPROVED YIELD LEARNING
Simplified Explanation: The patent application describes an integrated circuit on a production die that includes a device under test (DUT) cell array for voltage contrast detection of electrical opens on the die. The DUT transistor structures in the array have vias that are not connected to power or signal lines, ensuring they are isolated from other functioning transistors. A guard ring buffer is also included at the transition between the active transistor region and the DUT cell array.
- The integrated circuit on a production die includes a DUT cell array for voltage contrast detection of electrical opens.
- The DUT transistor structures have vias that are not connected to power or signal lines, ensuring isolation.
- A guard ring buffer is formed at the transition between the active transistor region and the DUT cell array.
Potential Applications: This technology can be applied in the semiconductor industry for testing and detecting electrical opens in production dies, ensuring the quality and reliability of integrated circuits.
Problems Solved: This technology addresses the need for efficient and accurate detection of electrical opens in production dies, improving the overall quality control process in semiconductor manufacturing.
Benefits: The technology offers improved reliability and quality control in semiconductor manufacturing, leading to higher performance and durability of integrated circuits.
Commercial Applications: Potential commercial applications include semiconductor manufacturing companies, quality control laboratories, and electronic device manufacturers looking to enhance the reliability of their products.
Prior Art: Readers can explore prior art related to voltage contrast detection in semiconductor testing, guard ring buffers in integrated circuits, and isolation techniques for transistor structures.
Frequently Updated Research: Stay updated on the latest advancements in voltage contrast detection techniques, isolation methods for transistor structures, and quality control processes in semiconductor manufacturing.
Questions about Integrated Circuits with DUT Cell Arrays: 1. How does the inclusion of guard ring buffers improve the reliability of voltage contrast detection in integrated circuits? 2. What are the potential challenges in implementing DUT cell arrays with isolated transistor structures in semiconductor manufacturing?
Original Abstract Submitted
an integrated circuit on a production die comprises a device under test (dut) cell array formed in a fill region on the production die, the dut cell array comprising a plurality of dut transistor structures configured for voltage contrast (vc) detection of electrical opens on the production die. the dut transistor structures comprise one or more vias that are not located on power lines or signal lines, such that the dut transistor structures are not connected to each other or to the electrically functioning transistors. a guard ring buffer is formed at a transition between the active transistor region and the dut cell array.
