Apple inc. (20240329933). NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS simplified abstract

NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS

Organization Name

apple inc.

Inventor(s)

Lei Wang of San Carlos CA (US)

Jaewon Shin of Los Altos CA (US)

Seungjin Lee of Los Altos CA (US)

Ji Liang Song of Cupertino CA (US)

Michael L. Liu of Los Altos CA (US)

Christopher L. Mills of Saratoga CA (US)

NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240329933 titled 'NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS

Simplified Explanation

The patent application describes a multiply-accumulator circuit with a main multiplier circuit that can operate in floating-point or integer mode, along with a supplemental multiplier circuit that operates only in integer mode. This design allows for faster multiply-add operations without significantly increasing the circuit's footprint.

• Main multiplier circuit can operate in floating-point or integer mode
• Supplemental multiplier circuit operates in integer mode only
• Faster multiply-add operations in integer mode
• No significant increase in circuit footprint

Key Features and Innovation

• Main multiplier circuit can switch between floating-point and integer mode
• Supplemental multiplier circuit operates exclusively in integer mode
• Accelerates multiply-add operations by performing two parallel operations in integer mode
• No additional shifters needed for the supplemental multiplier circuit

Potential Applications

This technology can be applied in various fields where fast multiply-add operations are required, such as signal processing, image processing, and scientific computing.

Problems Solved

• Accelerates multiply-add operations
• Reduces the need for additional shifters
• Improves efficiency in floating-point and integer mode operations

Benefits

• Faster processing speed
• Enhanced efficiency in multiply-add operations
• Compact design without significant increase in footprint

Commercial Applications

Potential commercial applications include:

• High-performance computing systems
• Digital signal processors
• Image and video processing applications

Prior Art

Readers can explore prior art related to multiply-accumulator circuits, floating-point operations, and integer mode multiplier circuits in the field of digital signal processing and computer architecture.

Frequently Updated Research

Stay updated on the latest advancements in multiply-accumulator circuits, floating-point operations, and integer mode multiplier circuits in digital signal processing and computer architecture research.

Questions about Multiply-Accumulator Circuits

What are the key advantages of using a multiply-accumulator circuit in signal processing applications?

A multiply-accumulator circuit offers the advantage of performing multiply-add operations efficiently, which is essential in signal processing applications where complex mathematical operations are required.

How does the design of the main and supplemental multiplier circuits contribute to the overall efficiency of the multiply-accumulator circuit?

The main multiplier circuit's ability to switch between floating-point and integer mode, along with the supplemental multiplier circuit operating exclusively in integer mode, allows for faster multiply-add operations without significantly increasing the circuit's footprint.

Original Abstract Submitted

embodiments of the present disclosure relate to a multiply-accumulator circuit that includes a main multiplier circuit operable in a floating-point mode or an integer mode and a supplemental multiplier circuit that operates in the integer mode. the main multiplier circuit generates a multiplied output that undergoes subsequent operations including a shifting operation in the floating-point mode whereas the supplemental multiplier generates another multiplied output that does not undergo any shifting operations. hence, in the integer mode, two parallel multiply-add operations may be performed by the two multiplier circuits, and therefore accelerate the multiply-adder operations. due to the lack of additional shifters associated with the supplemental multiplier circuit, the multiply-accumulator circuit does not have a significantly increased footprint.