18613401. NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE simplified abstract (ATOMERA INCORPORATED)
NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE
Organization Name
Inventor(s)
Donghun Kang of San Jose CA (US)
NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18613401 titled 'NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE
The semiconductor device described in the patent application includes gate stacks on a substrate, with trenches between them. Each gate stack consists of alternating layers of first and second semiconductor materials, with the second semiconductor material forming nanostructures. Source/drain regions are located within the trenches, along with insulating regions and dopant blocking superlattices.
- Gate stacks with alternating semiconductor materials and nanostructures
- Source/drain regions within trenches
- Insulating regions adjacent to layers of the first semiconductor material
- Dopant blocking superlattices adjacent to nanostructures
- Dopant blocking superlattices composed of stacked groups of layers
Potential Applications: - Advanced semiconductor devices - High-performance electronics - Nanotechnology research and development
Problems Solved: - Enhancing semiconductor device performance - Improving dopant control in nanostructures
Benefits: - Increased efficiency and speed in electronic devices - Enhanced control over dopant diffusion - Potential for smaller and more powerful devices
Commercial Applications: Title: Advanced Semiconductor Devices for High-Performance Electronics This technology could be utilized in the development of cutting-edge electronic devices for various industries, including telecommunications, computing, and consumer electronics. The improved performance and control offered by this innovation could lead to more efficient and powerful products in the market.
Questions about the Technology: 1. How does the use of dopant blocking superlattices impact the performance of the semiconductor device? 2. What are the potential challenges in scaling up this technology for mass production?
Original Abstract Submitted
A semiconductor device may include a substrate and spaced apart gate stacks on the substrate defining respective trenches therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The semiconductor device may further include respective source/drain regions within the trenches, respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and respective dopant blocking superlattices adjacent lateral ends of the nanostructures and flush with adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
