18613557. METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS simplified abstract (ATOMERA INCORPORATED)
Contents
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS
Organization Name
Inventor(s)
Donghun Kang of San Jose CA (US)
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18613557 titled 'METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS
The method described in the patent application involves creating a semiconductor device by forming gate stacks on a substrate, with nanostructures defined by alternating layers of first and second semiconductor materials.
- Gate stacks are spaced apart on the substrate, with trenches between adjacent gate stacks.
- Source/drain regions are formed within the trenches.
- Insulating regions are placed adjacent to the lateral ends of the layers of the first semiconductor material.
- Conductive contact liners are added in the trenches.
Potential Applications: - Advanced semiconductor manufacturing - High-performance electronic devices - Nanotechnology research and development
Problems Solved: - Enhancing the performance and efficiency of semiconductor devices - Improving the integration of nanostructures in electronic components
Benefits: - Increased speed and functionality of electronic devices - Enhanced reliability and durability of semiconductor components - Potential for miniaturization and energy efficiency
Commercial Applications: Title: "Innovative Semiconductor Device Manufacturing for Enhanced Performance" This technology could be utilized in the production of high-speed processors, memory chips, and other advanced electronic components. The market implications include improved competitiveness in the semiconductor industry and the potential for new product development opportunities.
Questions about Semiconductor Device Manufacturing: 1. How does the integration of nanostructures impact the performance of semiconductor devices? Nanostructures can enhance the conductivity and efficiency of electronic components by providing a more controlled pathway for electron flow.
2. What are the key advantages of using alternating layers of semiconductor materials in gate stacks? Alternating layers can optimize the properties of the gate stack, such as carrier mobility and threshold voltage, leading to improved device performance.
Original Abstract Submitted
A method for making a semiconductor device may include forming spaced apart gate stacks on a substrate with adjacent gate stacks defining a respective trench therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and respective conductive contact liners in the trenches.
