18600873. Falling-edge modulation signal receiver and falling-edge modulation signal sampling method simplified abstract (REALTEK SEMICONDUCTOR CORP.)
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Falling-edge modulation signal receiver and falling-edge modulation signal sampling method
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Falling-edge modulation signal receiver and falling-edge modulation signal sampling method - A simplified explanation of the abstract
This abstract first appeared for US patent application 18600873 titled 'Falling-edge modulation signal receiver and falling-edge modulation signal sampling method
Simplified Explanation: The patent application describes a receiver that processes an input signal with a duty cycle varying with the bit value, using oversampling and decision circuits to determine the value of the input signal.
Key Features and Innovation:
- Utilizes a phase-locked loop to generate an oversampling clock correlated with a signal clock.
- Oversampling circuit samples the input signal based on the oversampling clock to generate data groups corresponding to a single bit.
- Decision circuit determines the value of the single bit based on the number of data groups with a bit value of 1.
Potential Applications: This technology can be applied in communication systems, data transmission, and signal processing where accurate bit value determination is crucial.
Problems Solved: This technology addresses the challenge of accurately processing input signals with varying duty cycles to determine the correct bit value.
Benefits:
- Improved accuracy in determining the bit value of input signals.
- Enhanced signal processing capabilities.
- Increased reliability in communication systems.
Commercial Applications: Potential commercial applications include telecommunications equipment, data transmission devices, and signal processing systems for various industries.
Prior Art: Readers interested in prior art related to this technology could explore patents and research papers in the field of signal processing, communication systems, and modulation techniques.
Frequently Updated Research: Researchers in the field of signal processing and communication systems may be conducting studies on improving modulation signal receivers for more efficient data processing.
Questions about Falling-Edge Modulation Signal Receiver: 1. What are the key components of a falling-edge modulation signal receiver? 2. How does oversampling help in processing input signals with varying duty cycles?
Original Abstract Submitted
A falling-edge modulation signal receiver is configured to process an input signal having a duty cycle varying with a bit value of the input signal. The receiver includes: a phase-locked loop for generating an oversampling clock according to the input signal which correlates with a signal clock, wherein the oversampling frequency is not lower than five times the frequency of the signal clock; an oversampling circuit for sampling the input signal according to the oversampling clock and thereby generating multiple groups of data which as a whole is corresponding to a single bit of the input signal; and a decision circuit for ascertaining that X bits of the multiple groups of data are 1 and determining the value of the single bit according to the X. When the X is greater/less than a threshold, the decision circuit determines that the value of the single bit is 1/0.
