17981617. Programmable Accelerator for Data-Dependent, Irregular Operations simplified abstract (Google LLC)

Programmable Accelerator for Data-Dependent, Irregular Operations

Organization Name

Google LLC

Inventor(s)

Rahul Nagarajan of San Jose CA (US)

Suvinay Subramanian of Sunnyvale CA (US)

Arpith Chacko Jacob of Los Altos CA (US)

Christopher Leary of Sunnyvale CA (US)

Thomas James Norrie of San Jose CA (US)

Thejasvi Magudilu Vijayaraj of Santa Clara CA (US)

Hema Hariharan of Cupertino CA (US)

Programmable Accelerator for Data-Dependent, Irregular Operations - A simplified explanation of the abstract

This abstract first appeared for US patent application 17981617 titled 'Programmable Accelerator for Data-Dependent, Irregular Operations

Simplified Explanation

The abstract of this patent application describes an accelerator that can speed up operations involving data, irregular patterns, and memory usage. The accelerator includes a programmable engine for executing dynamic and irregular computations efficiently, along with a co-processor designed to accelerate predictable operations during its development and production.

• The patent application describes an accelerator capable of accelerating data dependent, irregular, and memory-bound operations.
• The accelerator includes a programmable engine for executing computations on-chip that are dynamic, irregular, and memory-bound.
• It also includes a co-processor that accelerates operations with predictable computational load and behavior during design and fabrication.

Potential Applications

This technology could have various applications in fields such as:

• High-performance computing
• Artificial intelligence and machine learning
• Data analytics and processing
• Graphics rendering and gaming

Problems Solved

The technology addresses several problems related to computational efficiency and performance, including:

• Accelerating operations that involve data dependencies, irregular patterns, and memory usage.
• Efficiently executing dynamic and irregular computations on-chip.
• Accelerating predictable operations during the design and fabrication process.

Benefits

The benefits of this technology include:

• Improved performance and efficiency in executing data-dependent, irregular, and memory-bound operations.
• Enhanced computational capabilities for dynamic and irregular computations.
• Accelerated predictable operations during the design and fabrication stages, leading to faster development and production.

Original Abstract Submitted

Aspects of the disclosure provide for an accelerator capable of accelerating data dependent, irregular, and/or memory-bound operations. An accelerator as described herein includes a programmable engine for efficiently executing computations on-chip that are dynamic, irregular, and/or memory-bound, in conjunction with a co-processor configured to accelerate operations that are predictable in computational load and behavior on the co-processor during design and fabrication.