18458075. SEMICONDUCTOR DEVICE simplified abstract (Kabushiki Kaisha Toshiba)
Contents
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Hiroko Nakamura of Yokohama Kanagawa (JP)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18458075 titled 'SEMICONDUCTOR DEVICE
The semiconductor device described in the abstract consists of two chips stacked on top of each other, with charged particle beams passing through through-holes in each chip. The first chip has a first substrate surface and a second substrate surface, while the second chip has a third substrate surface and a fourth substrate surface.
Key Features and Innovation:
- The device includes a plurality of first through-holes on the first chip and a plurality of second through-holes on the second chip for the charged particle beams to pass through.
- Different pairs of electrodes are provided on the first and fourth substrate surfaces to deflect the charged particle beams, creating a non-symmetrical electrode pattern between the two chips.
- The electrode patterns on the first and fourth substrate surfaces are not symmetrical, providing unique control over the charged particle beams.
Potential Applications:
- This technology could be used in advanced semiconductor manufacturing processes.
- It may find applications in particle beam lithography systems.
- The device could be utilized in research and development of new semiconductor materials.
Problems Solved:
- Provides precise control over charged particle beams in a semiconductor device.
- Allows for non-symmetrical electrode patterns for enhanced functionality.
- Enables advanced semiconductor manufacturing processes.
Benefits:
- Improved precision and control over charged particle beams.
- Enhanced functionality in semiconductor manufacturing.
- Potential for innovation in semiconductor research and development.
Commercial Applications:
- Title: Advanced Semiconductor Device with Controlled Charged Particle Beams
- This technology could be commercialized for use in semiconductor manufacturing facilities.
- It may have implications for companies involved in semiconductor research and development.
Questions about the technology: 1. How does the non-symmetrical electrode pattern impact the control of charged particle beams in the device? 2. What are the potential advantages of using charged particle beams in semiconductor manufacturing processes?
Original Abstract Submitted
A semiconductor device includes: a first chip having a first substrate surface, a second substrate surface provided on a side opposite to the first substrate surface, and a plurality of first through holes, a plurality of charged particle beams passing through the first through holes; a second chip provided on the first chip and having a third substrate surface facing the second substrate surface, a fourth substrate surface, and a plurality of second through holes provided on the first through holes, the charged particle beams passing through the second through holes; a plurality of first electrodes provided on the first substrate surface so as to be adjacent to the first through holes; a plurality of second electrodes provided on the first substrate surface; a plurality of third electrodes provided on the fourth substrate surface so as to be adjacent to the second through holes; and a plurality of fourth electrodes provided on the fourth substrate surface, wherein the first electrodes are a first pair of electrodes for deflecting the charged particle beams, the third electrodes are a second pair of electrodes for deflecting the charged particle beams, the second electrode and the fourth electrode are an additional electrode pattern other than the first pair of electrodes and the second pair of electrodes for deflecting the charged particle beams, and an electrode pattern formed by the first electrode and the second electrode on the first substrate surface and an electrode pattern formed by the third electrode and the fourth electrode on the fourth substrate surface are not symmetrical with respect to opposite substrate surfaces of the two chips.
