18431553. DISPLAY APPARATUS simplified abstract (Samsung Display Co., Ltd.)
Contents
DISPLAY APPARATUS
Organization Name
Inventor(s)
Youngjin Cho of Yongin-si (KR)
DISPLAY APPARATUS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18431553 titled 'DISPLAY APPARATUS
The display apparatus described in the patent application includes a substrate, a semiconductor layer with source, drain, and channel areas, a gate layer with a gate area, a first conductive layer connected to the gate area, and a second conductive layer covering the first layer and connected to the source area.
- Minimization or prevention of parasitic capacitor
- Substrate with semiconductor layer and gate layer
- Source, drain, and channel areas in the semiconductor layer
- First conductive layer connected to the gate area
- Second conductive layer covering the first layer and connected to the source area
Potential Applications: - Display technology - Semiconductor devices - Electronics industry
Problems Solved: - Minimizing or preventing parasitic capacitors - Enhancing display performance - Improving semiconductor device efficiency
Benefits: - Increased display quality - Enhanced semiconductor device functionality - Reduced interference in electronic circuits
Commercial Applications: Title: Advanced Display Technology for Enhanced Performance This technology can be applied in the development of high-quality displays for consumer electronics, medical devices, automotive displays, and industrial equipment. The improved efficiency and reduced interference make it a valuable innovation in the electronics market.
Questions about the technology: 1. How does the minimization of parasitic capacitors impact the performance of the display apparatus? - The minimization of parasitic capacitors helps improve the overall efficiency and performance of the display apparatus by reducing interference and enhancing signal clarity. 2. What are the potential challenges in implementing this technology on a large scale in the electronics industry? - Some potential challenges in implementing this technology on a large scale in the electronics industry may include production costs, scalability, and compatibility with existing manufacturing processes.
Original Abstract Submitted
Provided is a display apparatus, in which a parasitic capacitor is minimized or prevented, including a substrate, a semiconductor layer disposed on the substrate and including a source area and a drain area and a channel area disposed between the source area and the drain area, and a gate layer disposed on the semiconductor layer and including a gate area disposed on the channel area, a first conductive layer including a first subconductive layer disposed on the gate layer and electrically connected to the gate area, and a second conductive layer including a second subconductive layer disposed on the first conductive layer and electrically connected to the source area and covering the first subconductive layer.
