SK hynix Inc. patent applications on September 26th, 2024
Patent Applications by SK hynix Inc. on September 26th, 2024
SK hynix Inc.: 26 patent applications
SK hynix Inc. has applied for patents in the areas of H10B43/27 (6), G06F3/06 (4), H10B41/27 (4), H01L25/065 (2), H01L23/00 (2) H10B43/27 (5), G11C29/52 (1), H04N25/772 (1), H04N25/771 (1), H04N25/704 (1)
With keywords such as: data, raw, memory, signal, configured, layer, output, device, structure, and stack in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Jeong Jun LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F21/56
CPC Code(s): G06F3/0619
Abstract: an operation method of memory may include activating a first row that is selected in a first bank, activating a second row that is selected in a second bank, receiving an all-bank counting command, reading a first access count from memory cells of specific columns of the first row in response to the all-bank counting command, increasing the first access count, writing the increased first access count in the memory cells of the specific columns of the first row, reading a second access count from memory cells of specific columns of the second row in response to the all-bank counting command, increasing the second access count, and writing the increased second access count in the memory cells of the specific columns of the second row.
Inventor(s): Sae Gyeol CHOI of Icheon-si (KR) for sk hynix inc., Hye Mi KANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: a storage device may dynamically allocate, to a buffer, at least one among m number of buffer units each capable of storing at least one of a plurality of l2p mapping units. when receiving, from an external device, a mapping unit command requesting one or more target l2p mapping units among the plurality of l2p mapping units, the storage device may store the target l2p mapping units in the buffer before transmitting the target l2p mapping units to the external device.
Inventor(s): Ji Wook KIM of Gyeonggi-do (KR) for sk hynix inc., Won Kyoo LEE of Gyeonggi-do (KR) for sk hynix inc., Ie Ryung PARK of Gyeonggi-do (KR) for sk hynix inc., Jeong Won SEO of Gyeonggi-do (KR) for sk hynix inc., A Hyun LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: a data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2n, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is n, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not n.
Inventor(s): Dong Sop LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2n, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is n, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not n.
Inventor(s): Jae Yong SON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/07, G11C16/26
CPC Code(s): G06F11/076
Abstract: a semiconductor storage device searches for an optimal read voltage on the basis of an error bit variance for each second read voltage interval without performing repeated additional reads up to the limit of left and right cell difference probabilities. accordingly, the semiconductor storage device can detect an optimal read voltage rapidly and accurately by minimizing the number of reads for a memory cell, when performing a second read for determining the optimal read voltage.
Inventor(s): Ie Ryung PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F11/10, G06F11/14
CPC Code(s): G06F11/1016
Abstract: a data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2n, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is n, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not n.
Inventor(s): Ji Wook KIM of Gyeonggi-do (KR) for sk hynix inc., Won Kyoo LEE of Gyeonggi-do (KR) for sk hynix inc., Ie Ryung PARK of Gyeonggi-do (KR) for sk hynix inc., Jeong Won SEO of Gyeonggi-do (KR) for sk hynix inc., A Hyun LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/18, G06F9/48, G06F13/16
CPC Code(s): G06F13/18
Abstract: a data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2n, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is n, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not n.
Inventor(s): Joon Hong PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dae Han KWON of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F13/20
CPC Code(s): G06F13/20
Abstract: a semiconductor chip includes a first input/output control circuit configured to generate a first input/output switching signal that controls a first data input/output operation on a first data input/output group according to a first input voltage generated based on an operation voltage, and a second input/output control circuit configured to generate a second input/output switching signal that controls a second data input/output operation on a second data input/output group according to a second input voltage generated based on the operation voltage.
Inventor(s): Dong Gyun KIM of Gyeonggi-do (KR) for sk hynix inc., Jeong Yong SONG of Gyeonggi-do (KR) for sk hynix inc., Jae Yoon YOO of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T3/4015, G06T7/90
CPC Code(s): G06T3/4015
Abstract: an image signal processor and an image signal processing method are disclosed. the image signal processor includes a stripe pattern determiner configured to calculate a gradient index for each of a plurality of directions in a target kernel and determine whether the target kernel corresponds to a stripe pattern based on the gradient index for each of the plurality of directions, a pattern direction determiner configured to determine a pattern direction of the target kernel when the target kernel corresponds to the stripe pattern, and a demosaicing component configured to perform an interpolation operation based on the pattern direction of the target kernel.
Inventor(s): Cheol Jon JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Ik KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jun Hyeok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06T7/73, G06T5/00
CPC Code(s): G06T7/73
Abstract: an image signal processor for processing image signals and an image signal processing method for the same are disclosed. the image signal processor includes a directionality determiner configured to determine directionality of a target kernel including a target pixel, based on an angle between directions within the target kernel and a difference in directionality strength between the directions. the image signal processor also includes a pixel corrector configured to correct, when the target kernel has specific directionality according to a result of the directionality determination, the target pixel using pixels arranged in each of a plurality of directions having higher directionality strength than a predetermined directionality strength from among the directions within the target kernel.
20240321331. SEMICONDUCTOR DEVICES_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Il KIM of Yongin-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/22, G11C5/06, G11C7/10, G11C8/12
CPC Code(s): G11C7/222
Abstract: a semiconductor device includes a first rank and a second rank. the first rank operates in synchronization with a clock signal in response to a first rank selection signal, and the second rank operates in synchronization with the clock signal in response to a second rank selection signal. the first rank performs a termination operation without performing an internal control operation if the first rank selection signal maintains an enabled state in synchronization with a first edge and a second edge of the clock signal.
Inventor(s): Kwang Min LIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hee Youl LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10
CPC Code(s): G11C16/3427
Abstract: a semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. the memory cell array includes a plurality of memory blocks coupled to a common source line. the peripheral circuit performs a program operation on a memory block selected from among the memory blocks. the control logic controls the program operation of the peripheral circuit. the memory blocks are coupled to corresponding source select lines, respectively. the program operation includes a plurality of program loops, each including a channel precharge operation. during the channel precharge operation, the control logic controls the peripheral circuit so that the common source line floats and a voltage of a source select line coupled to an unselected memory block, among the memory blocks, is increased.
Inventor(s): Seon Woo HWANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seong Jin KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Hwan JI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C29/52, G11C7/10
CPC Code(s): G11C29/52
Abstract: a semiconductor apparatus includes a parity operation circuit, a write latch circuit, a data processing circuit and a write path. the parity operation circuit generates a parity signal by performing an operation on operation source data. the write latch circuit generates a write parity signal by latching the parity signal according to a delayed write signal. the data processing circuit outputs write data as the operation source data in a write operation, and delays the operation source data by a time required for operation of the parity signal and outputs it as delayed data. the write path writes the delay data and the write parity signal to a memory area in the write operation.
Inventor(s): Ki Yong LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/498, H01L23/00, H01L25/065, H10B80/00
CPC Code(s): H01L23/49838
Abstract: a semiconductor package includes a control chip and a memory stack mounted on a substrate, and first and second stack bonding wires. the memory stack includes first and second memory stacks. the substrate includes first and second bond fingers. the first and second bonding wires connect the first and second bond fingers to the first and second memory stack, respectively. a first electrical path connecting a first channel pad of the control chip to the first bond finger is longer than a second electrical path connecting a second channel pad of the control chip to the second bond finger. the first stack bonding wire is shorter than the second stack bonding wire.
Inventor(s): Sung Lae OH of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L23/538, H01L21/762, H01L21/768, H01L25/065, H01L29/06, H10B43/27
CPC Code(s): H01L23/5384
Abstract: a method for manufacturing a semiconductor device comprises: forming isolation layers in a front surface of an upper wafer substrate; forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate; forming a first dielectric layer that fills the through hole; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer; and forming a second wiring line coupled to the through via.
Inventor(s): Ki Yong LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seung Hyun LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyoung Min IM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/552, H01L23/31, H01L23/498
CPC Code(s): H01L23/552
Abstract: a semiconductor package including a shield layer and a method of manufacturing the same. the semiconductor package includes a package substrate, a semiconductor die, an encapsulant layer, and a shield layer. the semiconductor package includes a side that connects a first surface and second surface of the package substrate and includes recesses that are formed along an edge where the second surface and the side meet.
Inventor(s): Nam Jae LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/06, H01L27/088, H01L29/417, H01L29/423, H01L29/66
CPC Code(s): H01L29/0603
Abstract: a semiconductor device may include a silicide gate electrode that is disposed over a substrate, a first epitaxial pattern that protrudes from the substrate, a second epitaxial pattern that protrudes from the substrate, a silicide source contact that is connected to the substrate through the first epitaxial pattern and that is disposed at a level different from a level of the silicide gate electrode, and a silicide drain contact that is connected to the substrate through the second epitaxial pattern and that is disposed at a level different from the level of the silicide gate electrode.
20240323527. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Wook CHO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H04N23/67, G02B6/42, H01L27/146
CPC Code(s): H04N23/672
Abstract: an image sensing device includes: a plurality of photoelectric conversion elements included in a unit pixel and located in a substrate layer; an isolation structure configured to isolate the plurality of photoelectric conversion elements from photoelectric conversion elements included in another unit pixel; a first anti-reflection layer configured to overlap the plurality of photoelectric conversion elements and disposed to be in contact with one surface of the substrate layer; a light guide disposed between the plurality of photoelectric conversion elements and disposed to be in contact with one surface of the substrate layer and the first anti-reflection layer; a grid layer configured to overlap the isolation structure; and a second anti-reflection layer disposed to be in contact with the first anti-reflection layer, the light guide, and the grid layer, wherein the light guide includes a material having a refractive index smaller than a refractive index of the first anti-reflection layer.
Inventor(s): Cheol Jon JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/704, H04N25/46
CPC Code(s): H04N25/704
Abstract: an image signal processing system capable of performing image processing and an image signal processing method for the same are disclosed. the image signal processor includes an image binning “circuit” generates a down-scaled second image from a first image by summing pixel values of at least one pair of phase difference detection pixels and pixel values of color pixels in the first image. an extractor estimates pixel values of the phase difference detection pixels based on pixel values of the color pixels in a target kernel of the second image. a correction value is obtained by excluding pixel values estimated by the extractor from the target pixel obtained by summing the pixel values of the pair of phase difference detection pixels and the pixel values of the color pixels.
20240323567. IMAGE SENSOR AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Jung Soon SHIN of Gyeonggi-do (KR) for sk hynix inc., Seong Hee PARK of Gyeonggi-do (KR) for sk hynix inc., Ki Young KIM of Gyeonggi-do (KR) for sk hynix inc., Jong Eun KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/771, G06F17/16, H04N25/78
CPC Code(s): H04N25/771
Abstract: disclosed is an image sensor including a plurality of column lines, a plurality of pixels coupled to the plurality of column lines, and configured to output a plurality of pixel signals to the plurality of column lines in response to first control signals, and a plurality of memory cells coupled to the plurality of column lines, and configured to output a plurality of convolution signals, in which a plurality of data signals are reflected in the plurality of pixel signals, to the plurality of column lines in response to second control signals.
20240323568. IMAGE SENSOR AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Sun Young LEE of Gyeonggi-do (KR) for sk hynix inc., Jeong Eun SONG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/772, H03M1/34
CPC Code(s): H04N25/772
Abstract: disclosed is an image sensor including first and second pixels arranged in a first row, for outputting first and second pixel signals through first and third column lines during a unit row time; third and fourth pixels arranged in a second row, for outputting third and fourth pixel signals through second and fourth column lines during the unit row time; an alignment circuit for aligning the first to fourth pixel signals for each row, and outputting first to fourth alignment signals, according to control signals; a first signal conversion circuit for generating a first depth information signal corresponding to a difference in voltage levels between the first and second alignment signals, through one a/d conversion operation; and a second signal conversion circuit for generating a second depth information signal, corresponding to a difference in voltage levels between the third and fourth alignment signals, through one a/d conversion operation.
20240324200. SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE_simplified_abstract_(sk hynix inc.)
Inventor(s): Chang Woo KANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10B43/27, G11C16/08, H01L23/528, H10B41/10, H10B41/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a semiconductor device may include a stacked structure including a plurality of interlayer insulating layers and a plurality of horizontal line layers alternately stacked, a plurality of channel structures passing through the plurality of interlayer insulating layers and the plurality of horizontal line layers, and a first through electrode and a second through electrode passing through the plurality of interlayer insulating layers and the plurality of horizontal line layers and connected to the plurality of horizontal line layers. there may be provided a first logic structure which is disposed under the stacked structure and includes a first lower pass transistor connected to the first through electrode. in addition, there may be provided a second logic structure which is disposed on the stacked structure and includes a first upper pass transistor connected to the second through electrode.
Inventor(s): Jae Ho KIM of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/00, H10B43/35
CPC Code(s): H10B43/27
Abstract: provided is a memory device and a manufacturing method of the memory device. the memory device includes: a source line; a dummy stack structure located on the source line; a main stack structure located on the dummy stack structure; and a source contact in contact with the source line while penetrating the main stack structure and the dummy stack structure. the dummy stack structure includes: a first material layer located on the source line; and second material layers, blocking insulating layers, and dummy conductive layers, located on the first material layer. the main stack structure includes insulating layers and gate conductive layers, which are alternately stacked on the dummy stack structure.
20240324203. MEMORY DEVICE AND MANUFACTURING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Rho Gyu KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seok Min CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: there are provided a memory device and a manufacturing method thereof. the memory device includes: a first stack structure including a plurality of first interlayer insulating layers and a plurality of conductive layers for first word lines, which are alternately stacked; and a second stack structure including a plurality of second interlayer insulating layers and a plurality of conductive layers for second word lines, which are alternately stacked; a first etch stop layer disposed between the first stack structure and the second stack structure; and a plurality of first word line contacts extending to the inside of the first stack structure through the second stack structure and the first etch stop layer.
Inventor(s): In Ku KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a gate stack, a first data storage segment and a second data storage segment. the gate stack includes a first and second concave portions, which face opposite directions. the first and second t data storage segments correspond to the first and second concave portions.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/528, H10B41/10, H10B41/27, H10B41/40, H10B43/10, H10B43/40
CPC Code(s): H10B43/27
Abstract: there are provided a memory device and a manufacturing method of the memory device. the memory device includes: a first gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the first horizontal part; a first insulating pattern disposed between the first horizontal part and the second horizontal part of the first gate conductive pattern; and a second gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the second horizontal part of the second gate conductive pattern; a first gate contact structure extending vertically on a contact region, the first gate contact structure being in contact with the first gate conductive pattern while penetrating the third horizontal part of the first gate conductive pattern.
- SK hynix Inc.
- G06F3/06
- G06F21/56
- CPC G06F3/0619
- Sk hynix inc.
- CPC G06F3/0631
- CPC G06F3/0656
- CPC G06F3/0659
- G06F11/07
- G11C16/26
- CPC G06F11/076
- G06F11/10
- G06F11/14
- CPC G06F11/1016
- G06F13/18
- G06F9/48
- G06F13/16
- CPC G06F13/18
- G06F13/20
- CPC G06F13/20
- G06T3/4015
- G06T7/90
- CPC G06T3/4015
- G06T7/73
- G06T5/00
- CPC G06T7/73
- G11C7/22
- G11C5/06
- G11C7/10
- G11C8/12
- CPC G11C7/222
- G11C16/34
- G11C16/04
- G11C16/10
- CPC G11C16/3427
- G11C29/52
- CPC G11C29/52
- H01L23/498
- H01L23/00
- H01L25/065
- H10B80/00
- CPC H01L23/49838
- H01L23/538
- H01L21/762
- H01L21/768
- H01L29/06
- H10B43/27
- CPC H01L23/5384
- H01L23/552
- H01L23/31
- CPC H01L23/552
- H01L27/088
- H01L29/417
- H01L29/423
- H01L29/66
- CPC H01L29/0603
- H04N23/67
- G02B6/42
- H01L27/146
- CPC H04N23/672
- H04N25/704
- H04N25/46
- CPC H04N25/704
- H04N25/771
- G06F17/16
- H04N25/78
- CPC H04N25/771
- H04N25/772
- H03M1/34
- CPC H04N25/772
- G11C16/08
- H01L23/528
- H10B41/10
- H10B41/27
- H10B43/10
- CPC H10B43/27
- H10B43/35
- H10B41/40
- H10B43/40
