Kioxia corporation (20240321352). MEMORY DEVICE simplified abstract
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Ryu Ogiwara of Yokohama Kanagawa (JP)
Hidehiro Shiga of Yokohama Kanagawa (JP)
Daisaburo Takashima of Yokohama Kanagawa (JP)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240321352 titled 'MEMORY DEVICE
The abstract of this patent application describes a device with a memory cell and a sense amplification circuit that reads data from the memory cell based on voltage comparisons.
- Memory cell stores first data with three bits
- Sense amplification circuit compares bit line voltage to reference voltages
- Retains second data with a first code if voltage is equal to or lower than first reference voltage during a specific period
- Retains first data after the specific period
Potential Applications: - Data storage devices - Semiconductor technology - Memory systems
Problems Solved: - Efficient reading of data from memory cells - Accurate voltage comparisons for data retrieval
Benefits: - Improved data reading accuracy - Enhanced memory cell performance - Increased efficiency in data storage systems
Commercial Applications: Title: "Enhanced Memory Cell Technology for Data Storage Devices" This technology can be used in various data storage devices, improving their performance and efficiency. It can have significant implications in the semiconductor industry and memory system development.
Questions about Enhanced Memory Cell Technology for Data Storage Devices: 1. How does this technology improve data reading accuracy in memory cells? 2. What are the potential commercial applications of this innovation?
Frequently Updated Research: Stay updated on the latest advancements in memory cell technology and semiconductor devices to enhance data storage efficiency and performance.
Original Abstract Submitted
according to one embodiment, a device includes: a memory cell coupled to a bit line and configured to store first data including first, second, and third bits; and a sense amplification circuit configured to perform a first comparison between a bit line voltage and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on results of the first and second comparisons. the sense amplification circuit is configured to retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation to a first time point, and retain the first data after the first period.
