Qualcomm incorporated (20240321376). Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset simplified abstract
Contents
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset
Organization Name
Inventor(s)
Debarghya Dutta of Kolkata (IN)
Ramakoti Nimmakayala of Bangalore (IN)
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240321376 titled 'Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier Offset
The patent application describes a memory system with a scan path connected to sense amplifier output nodes. The scan path includes a clocked latch that captures a data-in signal when a clock signal is received during a scan operation. The clocked latch remains unclocked during a read operation to the memory. To prevent any changes in the data-in signal from affecting the read operation, the scan path incorporates at least one blocking logic gate between the clocked latch and the sense amplifier output node.
- The memory system includes a scan path with a clocked latch for capturing data during scan operations.
- The clocked latch remains unclocked during read operations to prevent interference with the data.
- Blocking logic gates are used in the scan path to prevent binary transitions in the data-in signal from affecting the read operation.
- This innovation ensures the integrity of data read from the memory by isolating the scan path during read operations.
- The technology enhances the reliability and accuracy of data retrieval in memory systems.
Potential Applications: - This technology can be applied in various memory systems such as RAM, ROM, and flash memory. - It can be utilized in data storage devices, embedded systems, and computer processors.
Problems Solved: - Prevents binary transitions in the data-in signal from impacting read operations. - Ensures the accuracy and reliability of data retrieval in memory systems.
Benefits: - Improved data integrity during read operations. - Enhanced reliability and accuracy in memory systems. - Increased efficiency in data storage and retrieval processes.
Commercial Applications: Title: Enhanced Memory System with Scan Path for Improved Data Integrity This technology can be commercially used in the development of high-performance memory systems for various applications such as data centers, IoT devices, and consumer electronics. The improved data integrity and reliability offered by this innovation can lead to faster and more efficient data processing, making it a valuable asset in the technology industry.
Questions about Memory System with Scan Path: 1. How does the clocked latch in the scan path improve data capture in memory systems? 2. What are the potential implications of using blocking logic gates in the scan path for data integrity in memory operations?
Original Abstract Submitted
a memory is provided with scan path coupled to sense amplifier output nodes. the scan path include a clocked latch that latches a data-in signal responsive to a clock signal during a scan operation to the memory. the clocked latch is not clocked during a read operation to the memory. to prevent a binary transition of the data-in signal from affecting the read operation, the scan path includes at least one blocking logic gate coupled between the clocked latch and the sense amplifier output node.
