Qualcomm incorporated (20240320140). SYSTEM MEMORY ADDRESS DECODING FOR INTERLEAVING ADDRESSES ACROSS PHYSICAL REGIONS OF A SYSTEM-ON-CHIP (SOC) AND ACROSS SHARED MEMORY RESOURCES IN A PROCESSOR-BASED SYSTEM simplified abstract
SYSTEM MEMORY ADDRESS DECODING FOR INTERLEAVING ADDRESSES ACROSS PHYSICAL REGIONS OF A SYSTEM-ON-CHIP (SOC) AND ACROSS SHARED MEMORY RESOURCES IN A PROCESSOR-BASED SYSTEM
Organization Name
Inventor(s)
Keith Robert Pflederer of Mountain View CA (US)
SYSTEM MEMORY ADDRESS DECODING FOR INTERLEAVING ADDRESSES ACROSS PHYSICAL REGIONS OF A SYSTEM-ON-CHIP (SOC) AND ACROSS SHARED MEMORY RESOURCES IN A PROCESSOR-BASED SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240320140 titled 'SYSTEM MEMORY ADDRESS DECODING FOR INTERLEAVING ADDRESSES ACROSS PHYSICAL REGIONS OF A SYSTEM-ON-CHIP (SOC) AND ACROSS SHARED MEMORY RESOURCES IN A PROCESSOR-BASED SYSTEM
Simplified Explanation: The patent application discusses a system memory address decoding method for interleaving addresses across physical regions of a system on a HIP (SoC) and shared memory resources in a processor-based system.
Key Features and Innovation:
- System on Chip (SoC) configured to determine the number of physical regions and shared memory resources available.
- Adaptive memory address decoding circuit to direct memory access requests to the proper shared memory resource.
- Ensures each address in the memory address range spans across all shared memory resources in the range.
Potential Applications: This technology can be applied in various computing systems where efficient memory address decoding and utilization of shared memory resources are crucial.
Problems Solved:
- Efficiently interleaving memory addresses across physical regions and shared memory resources.
- Ensuring optimal utilization of shared memory resources within a system.
Benefits:
- Improved memory access efficiency.
- Enhanced utilization of shared memory resources.
- Better performance in computing systems.
Commercial Applications: This technology could be valuable in the development of high-performance computing systems, data centers, and other applications requiring efficient memory management and utilization of shared resources.
Prior Art: Readers can explore prior patents related to memory address decoding, shared memory resource utilization, and system-on-chip architectures for further insights into this technology.
Frequently Updated Research: Stay updated on advancements in memory address decoding algorithms, shared memory resource management techniques, and system architecture optimizations for the latest developments in this field.
Questions about System Memory Address Decoding: 1. How does adaptive memory address decoding improve system performance? 2. What are the potential challenges in implementing interleaved memory addressing across physical regions and shared memory resources?
Original Abstract Submitted
system memory address decoding for interleaving addresses across physical regions of a system on hip (soc) and across shared memory resources in a processor based system and related hashing circuits are disclosed. in exemplary aspects, the soc is configured to discover, for every range of addresses, the number of physical regions and the number and/or size of the shared memory resources available including caches, snoop filters and memory interfaces within each physical region. the soc may include a system memory address decoding circuit that is configured to adaptively decode a memory address based on the memory address range in which the system address resides and then direct such memory access request to the proper shared memory resource so that each address in the memory address range spans across all of the shared memory resource in the range.
