Samsung electronics co., ltd. (20240321902). CHIP-ON-FILM PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract
Contents
CHIP-ON-FILM PACKAGE AND MANUFACTURING METHOD THEREOF
Organization Name
Inventor(s)
Yechung Chung of Suwon-si (KR)
CHIP-ON-FILM PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240321902 titled 'CHIP-ON-FILM PACKAGE AND MANUFACTURING METHOD THEREOF
The abstract describes a chip film package with a film substrate containing a chip mounting region, an inner lead bonding region, and an outer lead bonding region. The package also includes upper and lower surfaces, upper wiring patterns, and solder resist layers.
- Film package with chip mounting region, inner lead bonding region, and outer lead bonding region
- Upper and lower surfaces with wiring patterns and solder resist layers
- First upper wiring pattern extending from inner lead bonding region to outer lead bonding region
- Second upper wiring pattern spaced apart from the first in the first direction
- Upper solder resist layer covering the upper surface of the first upper wiring pattern
- Lower solder resist layer covering the upper surface of the lower wiring pattern
Potential Applications: - Semiconductor packaging - Integrated circuits - Electronics manufacturing
Problems Solved: - Efficient chip mounting and lead bonding - Protection of wiring patterns with solder resist layers
Benefits: - Improved reliability of electronic devices - Enhanced performance of integrated circuits
Commercial Applications: Title: Advanced Semiconductor Packaging Technology This technology can be used in the production of various electronic devices, such as smartphones, computers, and automotive electronics, enhancing their performance and reliability in the market.
Questions about Chip Film Package: 1. How does the chip film package improve the reliability of electronic devices? 2. What are the key features of the solder resist layers in the film package?
Frequently Updated Research: Researchers are constantly exploring new materials and techniques to further improve the efficiency and reliability of chip film packages in electronic devices. Stay updated on the latest advancements in semiconductor packaging technology for potential future applications.
Original Abstract Submitted
a chip of film package comprises a film substrate having a chip mounting region, an inner lead bonding region arranged within the chip mounting region, and an outer lead bonding region spaced apart from the inner lead bonding region in a first direction, and providing upper and lower surfaces opposite to each other, a first upper wiring pattern arranged on the upper surface of the film substrate and extending in the first direction from the inner lead bonding region to the outer lead bonding region, a second upper wiring pattern spaced apart from the first upper wiring pattern in the first direction, an upper solder resist layer covering an upper surface of the first upper wiring pattern; and a lower solder resist layer covering an upper surface of the lower wiring pattern.
