Samsung electronics co., ltd. (20240321381). MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOF simplified abstract
Contents
MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOF
Organization Name
Inventor(s)
MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240321381 titled 'MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOF
The memory device described in the patent application includes a memory cell array with pages, a page buffer circuit with latches, and control logic to manage data read and output operations.
- Memory device with memory cell array and page buffer circuit
- Page buffer circuit includes latches for each memory cell
- Control logic manages data read and output operations
- First hard decision data and first soft decision data controlled during read and output operations
- First hard decision data output after first soft decision data in first output mode
Potential Applications: - Data storage devices - Computer memory systems - Embedded systems
Problems Solved: - Efficient data read and output operations - Improved memory management
Benefits: - Faster data processing - Enhanced memory performance
Commercial Applications: Title: Advanced Memory Devices for High-Speed Data Processing This technology can be used in various commercial applications such as: - Solid-state drives - Data centers - High-performance computing systems
Questions about the technology: 1. How does the control logic optimize data read and output operations? - The control logic ensures that hard decision data and soft decision data are managed effectively during read and output processes. 2. What are the key advantages of using latches in the page buffer circuit? - Latches in the page buffer circuit help in storing and managing data efficiently.
Original Abstract Submitted
a memory device including: a memory cell array including pages each page including memory cells; a page buffer circuit including page buffers corresponding to the memory cells of each page, each of the page buffers including first through n-th latches; and a control logic to control first hard decision data and first soft decision data read in a first read operation on a first page to remain in a first page buffer during a second read operation on a second page, and control an output operation such that the first hard decision data is output after the first soft decision data is output when the memory device is set to a first output mode, wherein the first hard decision data is based on a normal read level and the first soft decision data is based on an offset read level read from the first page.
