Intel corporation (20240320000). UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS simplified abstract

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

Organization Name

intel corporation

Inventor(s)

Subramaniam Maiyuran of Gold River CA (US)

Jorge Parra of El Dorado Hills CA (US)

Ashutosh Garg of Folsom CA (US)

Chandra Gurram of Folsom CA (US)

Chunhui Mei of San Diego CA (US)

Durgesh Borkar of Folsom CA (US)

Shubra Marwaha of Folsom CA (US)

Supratim Pal of Folsom CA (US)

Varghese George of Folsom CA (US)

Wei Xiong of Fremont CA (US)

Yan Li of San Diego CA (US)

Yongsheng Liu of San Diego CA (US)

Dipankar Das of Pune (IN)

Sasikanth Avancha of Bangalore (IN)

Dharma Teja Vooturi of Jagtial (IN)

Naveen K. Mellempudi of Bangalore (IN)

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240320000 titled 'UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

Simplified Explanation: The patent application describes an apparatus designed to optimize the use of structured sparsity in systolic arrays. This apparatus includes a processor with a systolic array that can efficiently process data from multiple source registers, including both unpacked and structured source data. By identifying specific portions of the unpacked data to multiply with the structured data based on metadata, the processor can output the results to a destination register.

• Utilizes structured sparsity in systolic arrays
• Processor with systolic array receives data from multiple source registers
• Processes unpacked and structured source data efficiently
• Identifies portions of unpacked data to multiply with structured data based on metadata
• Outputs results to destination register

Potential Applications: - Signal processing - Image and video processing - Machine learning algorithms - Data compression techniques

Problems Solved: - Optimizing the use of structured sparsity in systolic arrays - Efficient processing of data from multiple source registers - Enhancing performance in various computational tasks

Benefits: - Improved efficiency in data processing - Enhanced performance in signal and image processing - Increased speed and accuracy in machine learning algorithms - Reduced computational complexity in data compression techniques

Commercial Applications: Title: "Optimizing Data Processing with Structured Sparsity in Systolic Arrays" This technology could be utilized in various industries such as: - Semiconductor manufacturing - Telecommunications - Artificial intelligence research and development - Data analytics companies

Prior Art: Prior art related to this technology may include research papers, patents, or academic studies on systolic arrays, structured sparsity, and data processing optimization techniques.

Frequently Updated Research: Researchers may be exploring new ways to enhance the efficiency and performance of systolic arrays using structured sparsity, as well as developing novel applications for this technology.

Questions about Structured Sparsity in Systolic Arrays: 1. How does the apparatus optimize the use of structured sparsity in systolic arrays? 2. What are the potential implications of this technology in the field of machine learning algorithms?

Original Abstract Submitted

an apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. the apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.