18374310. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18374310 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract includes a first redistribution structure with at least one redistribution layer and one insulating layer, a first semiconductor chip, a second semiconductor chip, and bumps between the redistribution structure and the chips. The redistribution layer features a detour redistribution line that overlaps a space between the chips, avoiding a stress concentration region.
- First redistribution structure with redistribution and insulating layers
- Detour redistribution line overlapping space between semiconductor chips
- Bumps connecting redistribution structure to semiconductor chips
- Stress concentration region avoided by detour redistribution line
- Circuitous extension of detour redistribution line between chips
- Potential Applications:**
- Semiconductor packaging industry - Electronics manufacturing - Integrated circuit design
- Problems Solved:**
- Reducing stress concentration in semiconductor packages - Improving signal integrity between chips - Enhancing reliability of semiconductor devices
- Benefits:**
- Increased performance of semiconductor packages - Enhanced durability and longevity of electronic devices - Improved manufacturing efficiency
- Commercial Applications:**
Title: Advanced Semiconductor Packaging Technology for Enhanced Performance This technology can be applied in various industries such as telecommunications, consumer electronics, and automotive electronics. It can improve the reliability and performance of electronic devices, leading to higher customer satisfaction and potentially increased market share for companies utilizing this innovation.
- Questions about Semiconductor Packaging Technology:**
1. How does the detour redistribution line contribute to reducing stress concentration in semiconductor packages? 2. What are the potential implications of this technology on the electronics manufacturing industry?
- Frequently Updated Research:**
Researchers are continuously exploring new materials and design techniques to further enhance the performance and reliability of semiconductor packages. Stay updated on the latest advancements in semiconductor packaging technology to ensure the competitiveness of electronic devices in the market.
Original Abstract Submitted
A semiconductor package includes: a first redistribution structure having a structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip disposed on the first redistribution structure; a second semiconductor chip disposed on the first redistribution structure; and bumps disposed between the first redistribution structure and the first semiconductor chip and between the first redistribution structure and the second semiconductor chip, wherein the at least one first redistribution layer includes a detour redistribution line disposed so that a portion of the detour redistribution line overlaps a space between the first and second semiconductor chips, and the detour redistribution line circuitously extends across the space between the first and second semiconductor chips so as not to overlap a stress concentration region partially overlapping a portion of the space between the first and second semiconductor chips, or extends into the stress concentration region.
